Confused on how to run

[NathanRizza]

Hello, I've been trying to run the HGDB vs code debugger and I'm unsure on how to proceed.

My process thus far: Obtained the symbol table from hgdb-vitis. Compiled the circuit with iverilog and produce an "a.out" file. run: vvp -M. -mlibhgdb a.out launch the hgdb debugger making sure the symbol table is named "debug.db"

doing this process I get the following: meanwhile I am trying to get an output similar to your demo like the following Any information on what I am doing wrong and/or a detailed guide on how to use this I would be appreciated. I haven't been able to find any documentation besides this website https://hgdb.dev/debugger/ but that doesn't show the workflow.

[Kuree]

Can you upload the symbol table file and a.out here so that I can take a look?

[NathanRizza]

Here you go. I have the symbol table labeled debug.db. https://mega.nz/folder/8TgmyITS#tJL3IOSWe2fsBT-DyAIg0g

[Kuree]

Thanks. I will take a look. vvp is less tested so I won't be surprised that hgdb runtime needs more fine tuning. In the meantime, you can try to use any supported commercial simulators if you have access to. They should work out of the box since they are more thoroughly tested.

Also reading through the symbol table, it seems like only i is successfully identified. I will also work on heuristics to identify the function argument num. If you know a way, please let me know.

[Kuree]

@NathanRizza Do you have a SystemVerilog-based testbench? It doesn't look like your a.out has any clock toggling. hgdb only works with RTL-level simulation.

[NathanRizza]

@Kuree I don't currently have a SystemVerilog testbench. I provided vitis with my c testbench but I assume it doesn't make that for me (I haven't found any in the solution folder)? Would I need to write a testbench by hand that interacts with the verilog generated by vitis?

[Kuree]

@NathanRizza It depends on your test environment setup. Vitis does have a C/RTL co-simulation setting. Unfortunately hgdb doesn't work with xsim (the simulator shipped with Vivado), since xsim doesn't have VPI support. However, if you have access to a commercial simulator, you can switch to that inside Vitis. Vitis will use it instead and you should be able to use hgdb by tweaking the command line flags.

[NathanRizza]

@Kuree So If I were to stick to iverilog I would just need to write a system verilog testbench?

[Kuree]

@NathanRizza That's right.

[NathanRizza]

Using the same process but adding a verilog testbench file into the iverilog a.out compilation I still do not get a working output. Is there any documentation on how to setup a functional workflow for hgdb, preferably with hgdb vitis? I think I'll need to switch either simulators or debuggers or both but I don't know which ones work for hgdb currently.

[Kuree]

I can create a document for Vitis + Xcelium + HGDB setup.

Can you share your a.out and testbench file? I feel like there might be some minor information missing.

As for non-Vitis setup, there are plenty. You can see the tests here: https://github.com/Kuree/hgdb/tree/master/tests/generators

[NathanRizza]

Here is the link to my latest a.out file https://mega.nz/file/Ie4DnZ7Q#MWCkBT5rcHT1_0fA4UsMLgiAVrf0XSQUfmltMjOAdAU

[Kuree]

I got it working with the Python version of hgdb-debugger. Here is what I did:

# assume everything is inside a python env
pip install libhgdb hgdb-debugger
# start the simulation
vvp -M. -mlibhgdb a.out
# in a separate terminal
hgdb localhost:8888 debug.db
> b pc.c:12
> c
> p num
> p $time

You can type help to see all available commands, which are modeled after gdb.

VSCode version should be similar. You have to open the pc.c file in VScode then set breakpoints. Make sure to use the sample launch.json here.