Error while running with `hgdb-replay` on VSCode

[rameloni]

Hello, I am debugging a circuit written in Chisel. I tried to use the hgdb-replay to replay the vcd trace. I already tried to use a verilator testbench and everything worked. However, I found writing a verilator testbench from scratch a bit complex while dealing with Chisel debugging, since it offers chiseltest which allows to create tests directly in the scala language. Thus, I wanted to use chiseltest in conjunction with hgdb:

1. create the symbol table using hgdb-firrtl
2. emit vcd from chiseltest
3. use hgdb-replay to rerun the simulation
4. run the vscode extension After I set the breakpoints in the source chisel code and I click the play button of the debugger it returns the following error:

   $ hgdb-replay myvcd.vcd
   [INFO][Wed Jan 24 10:27:42 2024] Building VCD database...
   [INFO][Wed Jan 24 10:27:42 2024] Initializing HGDB runtime...
   ERROR: failed to register system function $hgdb_assert_fail
   [INFO][Wed Jan 24 10:27:42 2024] Starting HGDB replay...
   [2024-01-24 10:27:47] [info] asio handle_accept error: asio.system:125 (Operation aborted.)
   [2024-01-24 10:27:47] [info] Error getting remote endpoint: asio.system:9 (Bad file descriptor)
   [2024-01-24 10:27:47] [info] asio async_shutdown error: asio.system:9 (Bad file descriptor)
   [2024-01-24 10:27:47] [error] handle_accept error: Operation aborted.
   [2024-01-24 10:27:47] [info] Stopping acceptance of new connections because the underlying transport is no longer listening.

[rameloni]

@Kuree I also have an issue while I use the Icarus simulation generated through chiseltest. It runs only for the first clock cycle and then it crashes. However, I do not have problems if I write my own Verilator testbench, but this is not ideal since requires additional code to write and time. I have my own chiseltest tests and it would be great to use them directly through hgdb-replay.

[Kuree]

Is it possible to provide the vcd? It's difficult to reproduce the issue without a buggy input.

[rameloni]

Is it possible to provide the vcd? It's difficult to reproduce the issue without a buggy input.

@Kuree Yes sure. I changed the extension to txt just to upload it on github. Adder.vcd.txt

This is the Module tested

// A n-bit adder with carry in and carry out
class Adder(val n: Int, val print: Boolean = false) extends Module {
  // IO interface
  val io = IO(new Bundle {
    val A = Input(UInt(n.W))
    val B = Input(UInt(n.W))
    val Cin = Input(UInt(1.W))

    val Sum = Output(UInt(n.W))
    val Cout = Output(Bool())
  })

  // Internal logic
  val FAs = Array.fill(n)(Module(new FullAdder()))
  val carry = Wire(Vec(n + 1, UInt(1.W)))
  val sum = Wire(Vec(n, Bool()))

  // first carry is the top level carry in
  carry(0) := io.Cin

  // wire up the ports of the full adders
  for (i <- 0 until n) {
    FAs(i).io.a := io.A(i)
    FAs(i).io.b := io.B(i)
    FAs(i).io.cin := carry(i)
    carry(i + 1) := FAs(i).io.cout
    sum(i) := FAs(i).io.sum.asBool
  }

  io.Sum := sum.asUInt
  io.Cout := carry(n)

  // For debugging purposes
  if (print) {
    System.out.println(
      s"Adder: ${n} ${io.A.name} ${io.B.name} ${io.Cin.name} ${io.Sum.name} ${io.Cout.name}"
    )
  }
}

[Kuree]

Thanks. Can you also attach the debug db file?

[rameloni]

Thanks. Can you also attach the debug db file?

@Kuree you can find all the needed files in the following zip archive. adder_hgdb.zip

[Kuree]

Thanks. I will take a look once I fix py311 issues.

[Kuree]

This bug happened because your dut does not have a clock signal. I've added some logic to detect that (best-effort).

[rameloni]

This bug happened because your dut does not have a clock signal. I've added some logic to detect that (best-effort).

I am sorry, but is it missing from chisel? Because I checked the output vcd and the fir file. Both have the clock.

[Kuree]

Full adder does not have a clock signal and the system use it as a reference instance unfortunately.

[rameloni]

Full adder does not have a clock signal and the system use it as a reference instance unfortunately.

I also tried other chisel examples (without combinational modules like the FullAdder), that still use the vcd dumped by chiseltest but I can't get them working. Do you have a simple example already made that I can reproduce?

[Kuree]

I don't have chisel set up on my current machine so I won't be able to give you an example of chiseltest. My guess why it would not work is that some module may still be combinational and confuses the pattern match. Can you provide me with an example of chiseltest that fail to run? I have some ideas where things can go wrong.

[rameloni]

I don't have chisel set up on my current machine so I won't be able to give you an example of chiseltest. My guess why it would not work is that some module may still be combinational and confuses the pattern match. Can you provide me with an example of chiseltest that fail to run? I have some ideas here things can go wrong.

@Kuree here you can find the examples, with chiseltests to run. I basically tried all of them, and none worked with vcd-rewrite. chisel-examples.zip