SinglePortSRAM chip_enable property typo

[philipaxer]

Hi,

this part in lib.py is a bug

    @property
    def chip_enable(self):
        return self.sram.__chip_enable

needs to be self.sram.chip_enable, without the underscore.

May I ask why you decided to implement the SRAM as part of the CPP logic? Wouldn't it be easier to desribe it in pure python? What if I need a multiport dual clock mem for instance?

regards Philip

[Kuree]

needs to be self.sram.chip_enable, without the underscore.

Thanks. I will take a look.

May I ask why you decided to implement the SRAM as part of the CPP logic? Wouldn't it be easier to desribe it in pure python? What if I need a multiport dual clock mem for instance?

I think that was part of my own experiment to compare the code generation performance between pure C++ and with python front-end. It turns out the performance is comparable, but C++ version is much more difficult to understand.

You're absolutely right that it is easier to describe it in pure python, and it should be done that way, as used by a project in my research group.

[philipaxer]

Thanks for the swift reply. Are there some standard example IPs available somewhere? I have a very hard time to go through the sources to wrap my brain around certain concepts, like the slices issue. Having some "standard" examples (like an async fifo or a uart controller) would help a lot. Most of the examples in the documentation are too simplistic for actual designs.

regards Philip

[Kuree]

Having some "standard" examples (like an async fifo or a uart controller) would help a lot.

Unfortunately we don't have "standard" examples yet. We do have an AXI-Lite controller but it is private. I will write some examples this week and make the AXI-Lite public if possible.

[Kuree]

I added a uart example here. I will try to finish async fifo by the end of this weekend.

Closing this issue for now. Please let me know if you have any more questions.

[philipaxer]

Thanks a lot, appreciated!