With the currernt beta Teensyduino, the T3.5 now actually has 256kb of memory instead of 192... So room for frame buffer.
This update, enables the frame buffer, including the DMA Async updates.
The Asynch support is a little more complicated on the T3.5 as
SPI1 and SPI2 don't have two DMA sources like they do on other boards.
So this version uses code similar to what was added to the SPI library
for asynch transfers.
With the currernt beta Teensyduino, the T3.5 now actually has 256kb of memory instead of 192... So room for frame buffer.
This update, enables the frame buffer, including the DMA Async updates. The Asynch support is a little more complicated on the T3.5 as SPI1 and SPI2 don't have two DMA sources like they do on other boards. So this version uses code similar to what was added to the SPI library for asynch transfers.