LDMX-Software / Ecal

Software module for digitizing, reconstructing, and vetoing within the ECal.
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DAQ Digitization Improvements #1

Closed tomeichlersmith closed 4 years ago

tomeichlersmith commented 4 years ago

There are several inaccuracies in the structure of the digitization and how the software emulates the HGCROC. Here are some notes on my plans for improving/fixing this pipeline.

Thresholds

There are three distinct thresholds that should be configurable. Listed from lowest to highest.

  1. Readout Threshold
    • Trying to exclude electronic noise
    • ~1MIP equivalent
  2. TOA Threshold
    • High enough to not fire continuously
    • Accurately pick out higher energy deposits in time
    • ~5 MIPs equivalent
  3. TOT Threshold
    • Only ~0.1% of hits go into this run mode
    • ~50 MIPs equivalent, ~95% full range of ADC
    • Allows us to still get a somewhat accurate energy measurement when going above the high end of our ADC readout range

Sim EDep --> Pulse Conversion

  1. Divide by effective electron-hole pair energy to get effective amount of charge generated in the Si
    • In 0.5mm thick Si, ~37k electrons per MIP or ~ 3.6eV per e-h pair
  2. Use this amount of charge to mimic the readout pulse
  3. Perform Readout in either TOT Mode or ADC Mode
    • Setting the max ADC range to 320 fC means there is about 5.8 fC per MIP and about 50 MIPs reaches the TOT threshold

TOT Mode

ADC Mode

tomeichlersmith commented 4 years ago

Will depend on updates to the Event Model that I'm doing in Issue #868

i.e. Development is being done so that ldmx-sw is on iss868 branch and Ecal is on iss1 branch:

git checkout iss868
git submodule update --init
cd Ecal
git checkout iss1
tomeichlersmith commented 4 years ago

@jmmans I have implemented a TOT measurement that uses a "drain rate" i.e. the rate that voltage drains off the chip after saturation. Then I use tot = voltage / drain_rate to get the TOT measurement and energy = tot * drain_rate * voltage_to_energy to reconstruct the energy. Two questions:

  1. Is this linear draining model approximately correct? I calculate TOT as how long the voltage takes to drain to zero, should it be until it drains below some other threshold?
  2. What is the drain rate of the chips? Right now for testing, I just set it to 25 MeV * (mV/MeV) / (10*25 ns) so that a very small number of high energy hits go above the maximum TOT can readout using 10 digi samples, but I know this isn't well motivated.
jmmans commented 4 years ago

Dear Tom,

Let's start with the ADC first, which is the most important.

The ADC is a 10-bit ADC. It has a programmable maximum range, but a typical choice appropriate for LDMX is 320 fC. Very roughly, 1 MIP is ~1 fC/100 um of silicon.

The TOT gets 'used' above a programmable threshold of say 300 fC. The range of the TOT extends to at least 4000 fC. The maximum TOT is 200ns and the TOT TDCs are internally 12 bits. That makes the least count ~1fC.

This is packed in 10 bits like this:

If TOT(true)<512, TOT(10) = TOT(true) If TOT(true)>=512, TOT(10) = 512+[ TOT(true)/8]

The SPEC is linked, but hard to pick through.

http://webusers.physics.umn.edu/~jmmans/tmp/HGCROC3_Spec_Working_Document_v1.5.pdf

Jeremy

On 9/8/20 2:45 PM, Tom Eichlersmith wrote:

@jmmans https://github.com/jmmans I have implemented a TOT measurement that uses a "drain rate" i.e. the rate that voltage drains off the chip after saturation. Then I use |tot = voltage / drain_rate| to get the TOT measurement and |energy = tot drain_rate voltage_to_energy| to reconstruct the energy. Two questions:

  1. Is this linear draining model approximately correct? I calculate TOT as how long the voltage takes to drain to zero, should it be until it drains below some other threshold?
  2. What is the drain rate of the chips? Right now for testing, I just set it to |25 MeV (mV/MeV) / (1025 ns)| so that a very small number of high energy hits go above the maximum TOT can readout using 10 digi samples, but I know this isn't well motivated.

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