GiiBii test suite

[sczther]

This is a pain to check, but I am trying my best. As I cannot verify on hardware, take these with a grain of salt. Found here.

Format "Name of tests" - <Passes in DMG mode? 1/0> ; <Passes in CGB mode? 1/0>

CPU corrupted_stop - 0 ; 0 corrupted_stop_2 - cannot test (no results) corrupted_stop_sound - cannot test (no results) cpu_registers_initial_dmg - 1 ; 1 cpu_registers_initial_gbc - N ; 0 (may be from a different CGB revision?) daa - cannot test (no results) halt_bug_test - 1 ; 1 halt_bug_timing - 1 ; 1 halt_if - 0 ; 0 halt_ret_adress - 1 ; 1 halt_strange_things - 1 ; 1 if_flag_cleared - 1 ; 1 speed_change_cancel (not pressed) - N ; 0 speed_change_cancel (pressed) - N ; 0 speed_change_timing_coarse - N ; 0 speed_change_timing_fine - N ; 0 stop_lcd_on_off - cannot test (not sure how to interpret results) stop_no_exit - cannot test (no results) undefined_opcodes - cannot test (no results) undefined_opcodes_2 - cannot test (no results)

DMA dma_copy_during_halt_speed - 0 ; 0 dma_halt_stop_speedchange - 0 ; 0 dma_irq dma_restart - 1 ; 1 (i hope, doesn't contain zero padding) dma_timing - 1 ; 1 (i hope, doesn't contain zero padding) dma_timing_2 - 1 ; 1 dma_timing_dblspeed - N ; 1 (i hope, doesn't contain zero padding) dma_timing_lcd_on - 0 ; 0 dma_valid_sources_dmg - 0 ; 0 dma_valid_sources_gbc - N ; 0 gdma_irq - N ; 0 gdma_timing_coarse - N ; 0 gdma_timing_fine - N ; 0 hdma_halt - N ; 0 hdma_modify_adress - N ; 1 hdma_start_1 - N ; 0 hdma_start_2 - N ; 0 hdma_start_3 - N ; 0 hdma_timing_fine - N ; 0 hdma_valid_dest_swap_bank - N ; 1 hdma_valid_sources - N ; 0

Interrupts halt_exit_timings_ime_disabled_dmg_mode - 1 ; 1 halt_exit_timings_ime_disabled_cgb_mode - N ; 1 halt_exit_timings_ime_enabled_dmg_mode - 1 ; 1 halt_exit_timings_ime_enabled_cgb_mode - N ; 1 int_timing_halt_dmg_mode - 1 ; 1 int_timing_halt_cgb_mode - N ; 1 int_timing_no_halt_dmg_mode - 1 ; 1 int_timing_no_halt_cgb_mode - N ; 1 joy_interrupt - NOT joy_interrupt_manual - NOT joy_interrupt_manual_delay - NOT lcd_irq_delay_timer_halt_dmg_mode - 1 ; 1 lcd_irq_delay_timer_halt_gbc_mode - N ; 1 lcd_irq_delay_timer_no_halt_dmg_mode - 1 ; 1 lcd_irq_delay_timer_no_halt_gbc_mode - N ; 1 serial_int_handle_timing_dmg_mode - 1 ; 1 serial_int_handle_timing_gbc_mode - N ; 1 set_clear_ime_delays - 1 ; 1 timer_int_handle_timing_dmg_mode - 1 ; 1 timer_int_handle_timing_gbc_mode - N ; 1 vbl_irq_delay_timer_dmg_mode - 1 ; 1 vbl_irq_delay_timer_gbc_mode - N ; 0

LCD TODO

Memory echo_ram_read - 0 ; 1 echo_ram_write - 0 ; 1 misc_rw_registers_gbc_mode - N ; 0 misc_rw_registers_gb_mode - 1 ; 1 oam_echo_ram_lcd_on - 1 ; 0 oam_echo_ram_read - 1 ; 0 oam_echo_ram_read_2 - 1 ; 0 oam_echo_ram_read_gbc_dmg_mode - N ; 0 timer_rw_regs - 1 ; 1

Serial sc_change_freq_gbc - N ; 0 sio_irq_delay - 0 ; 0

Sound div_resets_sound_test - cannot test (no results) fade_double_speed - N ; 1 (I hope, would not trust my ears, both sounded right)

Timers TODO

Video bg_disabled_dmg - cannot test (no results) bg_disabled_dmg_wx - cannot test (no results) bg_disabled_gbc - cannot test (no results)

I will do more as I have time.

[sczther]

Timers

div_reset_65k - 1 ; 1 div_reset_div - 1 ; 1 div_reset_serial - 1 ; 1 div_resets_tima_4k - 1 ; 1 div_resets_tima_4k_2 - 1 ; 1 div_resets_tima_16k - 1 ; 1 div_resets_tima_65k - 1 ; 1 div_resets_tima_262k - 1 ; 1 div_resets_timer - 0 ; 0 - Now passes div_resets_timer_owerflow - 1 ; 1 div_reset_timing - 1 ; 1 div_reset_when_inc - 1 ; 1 sys_clock_init_dmg_mode - 0 ; 0 - Now passes sys_clock_init_cgb_mode N ; 0 Now passes in CGB mode, doesn't pass in AGB mode (don't have a AGB GBC bootrom)

tested as of todays master, failures retested as of ver 13.3

[sczther]

DMA (restested on 13.3) dma_copy_during_halt_speed - 0 ; 0 dma_halt_stop_speedchange - 0 ; 1 dma_irq - 1 ; 1 dma_restart - 1 ; 1 dma_timing - 1 ; 1 dma_timing_2 - 1 ; 1 dma_timing_dblspeed - N ; 1 dma_timing_lcd_on - 0 ; 1 dma_valid_sources_dmg - 0 ; 0 dma_valid_sources_gbc - N ; 0 gdma_irq - N ; 1 gdma_timing_coarse - N ; 0 gdma_timing_fine - N ; 0 hdma_halt - N ; 0 hdma_modify_adress - N ; 1 hdma_start_1 - N ; 0 hdma_start_2 - N ; 1 hdma_start_3 - N ; 0 hdma_timing_fine - N ; 0 hdma_valid_dest_swap_bank - N ; 1 hdma_valid_sources - N ; 0

CGB DMA got a bit better! :)

[sczther]

Memory (restested on 13.3) echo_ram_read - 0 ; 1 echo_ram_write - 0 ; 1 misc_rw_registers_gbc_mode - N ; 0 misc_rw_registers_gb_mode - 1 ; 1 oam_echo_ram_lcd_on - 1 ; 0 oam_echo_ram_read - 1 ; 0 oam_echo_ram_read_2 - 1 ; 0 oam_echo_ram_read_gbc_dmg_mode - N ; 0 timer_rw_regs - 1 ; 1

No change

[LIJI32]

How do I read these results? 1 is pass 0 is fail? DMG first CGB second?

[sczther]

Yep :)

[sczther]

LCD (tested on 13.3)

last_ly_clocks - 1 ; 1 last_ly_ly_change - 1 ; 0 ly_clocks - 1 ; 1 vertical_refresh_clocks - 1 ; 1 power on off: lcd_poweroff_wait - not sure what I should be seeing lcd_poweron_state - 1 ; 1 only_60fps - 1 ; 1 more_than_60fps - 1 ; 1 only_2_3_frames - 0 ; 0 only_2_3_frames_stopdraw - 0 ; 0 only_2_3_frames_switchpal - 0 ; 0 mode2: mode2_oam_timing_spr_dis_dmg_mode - 1 ; 1 mode2_oam_timing_spr_dis_gbc_mode - N ; 0 mode2_oam_timing_spr_en_dmg_mode - 0 ; 1 mode2_oam_timing_spr_en_gbc_mode - N ; 0 mode2_read_oam_spr_dis_dmg_mode - 1 ; 1 mode2_read_oam_spr_dis_gbc_mode - N ; 1 mode2_read_oam_spr_en_dmg_mode - 1 ; 1 mode2_read_oam_spr_en_gbc_mode - N ; 1 mode2_stat_timing_spr_dis_dmg_mode - 0 ; 1 mode2_stat_timing_spr_dis_dmg_mode_8x16 - 0 ; 0 mode2_stat_timing_spr_dis_gbc_mode - N ; 0 mode2_stat_timing_spr_dis_gbc_mode_8x16 - N ; 0 mode2_stat_timing_spr_en_dmg_mode - 0 ; 0 mode2_stat_timing_spr_en_dmg_mode_8x16 - 1 ; 0 mode2_stat_timing_spr_en_gbc_mode - N ; 0 mode2_stat_timing_spr_en_gbc_mode_8x16 - N ; 0 mode3: mode3_stat_timing_spr_en_gbc_mode_8x16 - N ; 0

[sczther]

Continuing the LCD tests (on 13.3) ly_equals_lyc: test name | DMG | CGB alt_if_timings_lyc_1_143_dmg_mode | 1 | 1 alt_if_timings_lyc_1_143_gbc_mode | N | 1 alt_if_timings_lyc_2_144_dmg_mode | 1 | 1 alt_if_timings_lyc_2_144_gbc_mode | N | 1 alt_ly_timings_dmg_mode | 1 | 1 alt_ly_timings_gbc_mode | N | 0 if_timings_lyc_0_dmg_mode | 1 | 1 if_timings_lyc_0_gbc_mode | N | 1 if_timings_lyc_152_153_dmg_mode | 1 | 1 if_timings_lyc_152_153_gbc_mode | N | 1 ly_timings_lyc_0_dmg_mode | 1 | 1 ly_timings_lyc_0_gbc_mode | N | 0 ly_timings_lyc_1_143_dmg_mode | 1 | 1 ly_timings_lyc_1_143_gbc_mode | N | 0 ly_timings_lyc_2_144_dmg_mode | 1 | 1 ly_timings_lyc_2_144_gbc_mode | N | 0 ly_timings_lyc_152_153_dmg_mode | 1 | 1 ly_timings_lyc_152_153_gbc_mode | N | 0 stat_timings_lyc_0_dmg_mode | 1 | 1 stat_timings_lyc_0_gbc_mode | N | 1 stat_timings_lyc_1_143_dmg_mode | 1 | 1 stat_timings_lyc_1_143_gbc_mode | N | 1 stat_timings_lyc_2_144_dmg_mode | 1 | 1 stat_timings_lyc_2_144_gbc_mode | N | 1 stat_timings_lyc_152_153_dmg_mode | 1 | 1 stat_timings_lyc_152_153_gbc_mode | N | 1

[sczther]

Serial (on today's 13.6+ source): sc_change_freq_gbc - N ; 0 sio_irq_delay - 1 ; 1

[sczther]

sameboy_tests.ods Compiled all of the tests into a table and went through all the fails (did not retest passes). There still seems to be quite a lot of things failing, although some may be from model differences not known at the time.