LaurentCabaret / pyVhdl2Sch

pyVhdl2sch is a python based VHDL to (pdf) schematic converter
BSD 2-Clause "Simplified" License
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vhdl parsing quite sensible to coding style #1

Closed heikoengel closed 4 years ago

heikoengel commented 10 years ago

Hi, very nice project, can be really helpful!! Unfortunately the line-based vhdl parsing is quite sensitive to coding style:

works:

entity test is port (
  a : in std_logic;
  b : in std_logic;
  c : out std_logic );
end test;

does not work:

entity test is port 
  (
    a : in std_logic;
    b : in std_logic;
    c : out std_logic
  );
end test;

does not work:

entity test is port (
    a : in std_logic;
    b : in std_logic;
    c : out std_logic
  );
LaurentCabaret commented 10 years ago

Thank you!

I am working on that.

LaurentCabaret commented 10 years ago

Fixed, thanks!

heikoengel commented 10 years ago

sorry, not really fixed :( now this throws an exception:

entity test is port (
    a : in std_logic_vector(1 downto 0);
    b : in std_logic;
    c : out std_logic
  );
end test;

I'm not sure if this way of parsing VHDL can cover all cases... Additionally, you only check for std_logic, std_logic_vectors and integer ports. What about signed/unsigned/records/custom or any of the simulation-only types...

LaurentCabaret commented 10 years ago

Ok, I'll add theses this evening. Thanks

LaurentCabaret commented 10 years ago

Thank you again.

vhdl_reader now (c2b7cb4) add space around each symbol '(', ')', ';' and supress space around '-'

I let the issue open in case of new coding style errors.

Laurent

heikoengel commented 10 years ago

The provided examples are working now, but these are only a few cases of all possible options to write VHDL. I still think a line-based parsing does not got well with VHDL... Try this one:

entity
test
  is 
    port  --port
    ( --(
a
: --;;;
in 
std_logic_vector
(   
1
downto
0
  );
    b : in std_logic;
    c : out std_logic
  )

  ;
end
test;

sure, it's not nice nor easily readable VHDL code but still valid...

LaurentCabaret commented 10 years ago

i agree with you.

so (for the moment) i decided to put all the vhdl file on one line (after removing comments) and i reformat the code as needed

LaurentCabaret commented 10 years ago

I rewrote parse_vhdl_file() to take into account your remarks and reduce the syntax impact.

i'll work on extract_wire() soon in the same way

Laurent

LaurentCabaret commented 4 years ago

No new coding style request since a long time. I close the issue