/pyVhdl2Sch$ git diff
diff --git a/file_manager/vhdl_reader.py b/file_manager/vhdl_reader.py
index f9576ca..9933442 100644
--- a/file_manager/vhdl_reader.py
+++ b/file_manager/vhdl_reader.py
@@ -99,10 +99,10 @@ class Vhdl_reader:
if wire_type == "integer":
nb_wires = 32
else:
if wire_type == "std_logic":
if wire_type == "std_logic" or wire_type == "std_ulogic":
nb_wires = 1
else:
if wire_type == "std_logic_vector":
if wire_type == "std_logic_vector" or wire_type == "std_ulogic_vector" or wire_type == "signed" or wire_type == "unsigned":
bus_direction = real_words[5].lower()
bus_description = text.split("(")[1].split(")")[0]
if bus_direction == "downto":
diff --git a/pyV2S.py b/pyV2S.py
index 8cccdf0..ced8fd6 100755
--- a/pyV2S.py
+++ b/pyV2S.py
@@ -1,4 +1,4 @@
-#!/usr/bin/python
+#!/usr/bin/env python
-- coding: utf-8 --
Maybe you can enhance the skript to use the data type instead the number of wires for unknown data types?
I use a lot of vhdl-recods defined in packages in my projects, so the number of wires is difficult to determine.
LaurentCabaret
commented
9 years ago
/pyVhdl2Sch$ git diff diff --git a/file_manager/vhdl_reader.py b/file_manager/vhdl_reader.py index f9576ca..9933442 100644 --- a/file_manager/vhdl_reader.py +++ b/file_manager/vhdl_reader.py @@ -99,10 +99,10 @@ class Vhdl_reader: if wire_type == "integer": nb_wires = 32 else:
-- coding: utf-8 --
Maybe you can enhance the skript to use the data type instead the number of wires for unknown data types? I use a lot of vhdl-recods defined in packages in my projects, so the number of wires is difficult to determine.
regards, Bart