PDF generation fails with unclear error when a line is wrong

[cosmith]

> python pyV2S.py cyclic8bit.vhd

Traceback (most recent call last):
  File "pyV2S.py", line 29, in <module>
    reader = Vhdl_reader(filename, options)
  File "/Users/corentin/projects/pyVhdl2Sch/file_manager/vhdl_reader.py", line 31, in __init__
    self.parse_entity_part()
  File "/Users/corentin/projects/pyVhdl2Sch/file_manager/vhdl_reader.py", line 107, in parse_entity_part
    self.extract_wire(raw_line)
  File "/Users/corentin/projects/pyVhdl2Sch/file_manager/vhdl_reader.py", line 141, in extract_wire
    bus_direction = vhdl_wire_words[6].lower()
IndexError: list index out of range

With

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ShiftRegister is
    Port ( CLK : in STD_LOGIC;
        Output : out STD_LOGIC_VECTOR); -- missing `(7 downto 0)` here
end ShiftRegister;

architecture Behavioral of ShiftRegister is

signal Q : STD_LOGIC_VECTOR (7 downto 0) := "10011000";

begin

Output <= Q;

    process (CLK)
    begin
        if (CLK'event and CLK = '1') then
            Q(7 downto 0) <= Q(6 downto 0) & Q(7);
        end if;
    end process;

end Behavioral;

There should probably be some type of error checking before trying to access vhdl_wire_words[6]

[LaurentCabaret]

Is it better for you now ?