Generation of TestBench on simple code fails

[Viq111]

Using vhd file:

entity MUX is
    Port ( RGB : out STD_LOGIC_VECTOR (0 to 2) );
end MUX;

architecture Behavioral of MUX is
begin
    RGB <= "100";
end Behavioral;

This is generated RGB : OUT STD_LOGIC_VECTOR(0 downto 0) but should be: RGB : OUT STD_LOGIC_VECTOR(0 to 2). It happens twice in the code

[Viq111]

Same for INTEGER which returns INTEGER(0 downto 0)

[LaurentCabaret]

Fixed thanks!