Develop/mgg address decode

[mggates39]

This should do the whole memory map with the most possible external RAM available

[LegalizeAdulthood]

I feel like we can do this with fewer chips if we use another '138 instead of all the glue gates. This is what I see in this design:

• 74138 (2)
• 15 2-input AND (4)
• 2 2-input NAND (1)
• 5 inverters (1)
• 1 2-input OR (1)
• 2 2-input NOR (1)
• 1 2-input XOR (1)

That's a chip count of 11. I think the chip count can be reduced this by using the enables on the '138s as part of the address decode. Even then, I think some additional glue will be needed but if you look at inventory-counts.txt you'll see that I have some chips that can simplify the multi-level logic into a single level, e.g. 8-input NAND, 3-input NAND, 3-input OR.

It's not right to use /AS as an enable on the '138s because /AS is only active while multiplexing the low 8 bits of the address. The /AS should be used to drive a 373 latch to hold the A0-A7 stable while the remainder of the cycle proceeds. The full address (and therefore the chip enables) need to stay active for the remainder of the cycle.

Addresses 0x02, 0x03 and 0xA through 0xF should not be mapped to RAM because they are intentionally left open for adding other peripherals, perhaps an I2C interface or additional PIAs. In my notebook design sketch I was planning on bringing out enables to a header for the additional address pairs starting at 0x02, 0x0A, 0x0C and 0x0E. (My design was already doing the decoding, so bringing these enables out was essentially free.) This is a "nice to have" and not stated as a design requirement, but something I was thinking would make the board more extensible for those who want to add additional peripherals without forcing them to bit bang it through the two 8-bit parallel ports.

[mggates39]

I am sure we can. use fewer chips. I was just throwing out what stuck. I had not tried to reduce it yet based on the available chiops. I just wanted to get something that worked. Plus it was after 1 this morning and I had to stop sometime.

As for using AS to drive the '138s, according to the timing diagram the entire address is stable during Address Strobe (AS) High. (See figure 4 in MC146805E2_1983.pdf) If you are using it to drive the address latch, then it should still be valid to drive the '138s

Removing the address $0002-$0003 and $000A-$000F from RAM 1 is easy. Changing them over to have enables for the address pairs mentioned is simple enough.

I will update the design file accrding to the notes you have given and give you another PR when I am done.

[LegalizeAdulthood]

Yes, AS is valid during the entire address portion of the cycle, but it's not asserted during the data portion of the cycle. You have to keep driving the chip select through the entire memory cycle not just the address portion of the memory cycle. Look at the circuit diagram associated with the ASSIST05 monitor:

AS is used to drive the latch and not the '138 used for address decoding to generate the chip selects. They do use DS (data strobe) as an enable to the ACIA chip.

[LegalizeAdulthood]

From the data sheet:

Address strobe (AS) is an output strobe used to indicate the presence of an address on the 8-bit multiplexed bus. The AS line is used to demultiplex the eight least significant address bits from the data bus. A latch controlled by address strobe should capture addresses on the negative edge.

This is also clear from looking at the memory cycle diagram:

Peripheral and memory chips must remain selected until the falling edge of DS.

[mggates39]

So then latching a 'valid address' to drive the decoding could be done with a flip-flop that triggers on the rising edge of As and resets on the falling edge of DS. That along with an actual latching buffer for the address lines would tie it all together.

[LegalizeAdulthood]

I think you're making it more complicated than it needs to be; look at the example ASSIST05 circuit above. A single '373 is all that is needed and is exactly as described in the documentation for AS. You see this replicated throughout the designs in the 6805 User Manual, see PDF pages 66 and 111.