Implement basic address decode design - Githubissues

LegalizeAdulthood / 6805_SBC

A single board computer built around the Motorola 6805 CPU

GNU General Public License v2.0

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Implement basic address decode design #4

Closed LegalizeAdulthood closed 2 years ago

LegalizeAdulthood commented 2 years ago

Add 74138s to do basic address decoding in stages:
- Select 1K ranges of 8K address space
- For $0000-$0800 bottom 1K range, select 128 byte ($7F) chunks
- For $0000-$007F bottom 128 byte range, select 16 byte ($F) chunks
- For $0000-$000F bottom 16 byte range, select 2 byte chunks for ACIA and 4 2-byte pairs P1-P4 for external expansion.
- For $0100-$017F 128 byte range, select 16 byte ($F) chunks
- Map $0100-$010F 16 byte chunk to RTC
- Map $0080-$00FF to RAM1
- Map $0110-$07FF to RAM1
- Map $0800-$0FFF to RAM2
- Map $1000-$1FFF to ROM
Add test cases for all chip selects

This design is a little heavy on '138s, but everything is functional.

To do:

See about reducing chip count by using 2nd RTC CS input
See about reducing chip count by replacing the 138 for A12-A10 with a few gates, since ~A12 = ~ROMCS and ~(~A12 & A11) = ~RAM2CS
See about reducing chip count by using address lines for '138 enable inputs; the '138s on A6-A4 each only use a single output