LiamSkirrow / verilogtree

Print out the modular hierarchy of a Verilog design
MIT License
0 stars 0 forks source link

Replace current for loops with STL iterators #13

Open LiamSkirrow opened 1 year ago

LiamSkirrow commented 1 year ago

Using actual iterators from the templates themselves is probably better practice, should probably go in and make the replacement eventually.