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LiamSkirrow / verilogtree

Print out the modular hierarchy of a Verilog design
MIT License
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Include any unsupported syntax in README #15

Closed LiamSkirrow closed 10 months ago

LiamSkirrow commented 1 year ago

Anything that's valid Verilog, but is not supported by the current version of verilogtree should be clearly documented in its own little section of the README.

LiamSkirrow commented 1 year ago

At least for v0.1.0, I'm probably not going to support syntax like

ibex_ex_block #(
    .RV32M          (RV32M),
    .RV32B          (RV32B),
    .BranchTargetALU(BranchTargetALU)
  ) ex_block_i (
    .clk_i (clk_i),
    .rst_ni(rst_ni),

where the instance name can be arbitrarily far beyond the module name due to SystemVerilog parameters.

LiamSkirrow commented 1 year ago

Also likely won't be supporting this syntax for module declarations:

module ibex_core import ibex_pkg::*; #(
LiamSkirrow commented 1 year ago

I need to decide whether I will perform any detection of the above cases, since simply ignoring them as the regex will naturally do could cause verilogtree to crash if it ever performs a lookup for a module it has skipped over.

The above case regarding the parameters in the module instantiation (2 comments up from this one) would likely be quite easy to account for. Whereas the case detailed in the comment immediately above this one is probably a little outside the scope of verilogtree and would just be too hard to detect.

TODO: make an issue for the above case(s)