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LiamSkirrow / verilogtree

Print out the modular hierarchy of a Verilog design
MIT License
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Optionally space out lines in the output text #24

Open LiamSkirrow opened 1 year ago

LiamSkirrow commented 1 year ago

Give the ability to add x many newlines between each level of the tree, space it out a bit more to make the output less dense for very busy hierarchies with long module/instance names.