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LiamSkirrow / verilogtree

Print out the modular hierarchy of a Verilog design
MIT License
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Parse 'ifdefs and 'defines #27

Open LiamSkirrow opened 1 year ago

LiamSkirrow commented 1 year ago

Should probably (eventually) include ability to read `ifdefs since currently an instantiated function will be included in the hierarchy even though it may be ifdef'd away. Would need to parse `defines and actually determine on the fly whether certain modules would be instantiated. Alternatively give ability to include a `define file, so user can see what the hierarchy would look like with/without particular `defines.

LiamSkirrow commented 1 year ago

Instead of dynamically calculating how many module instances would be generated, simply flag any given instance as generated in the tree output, the user will then know that it's a generated module. Figuring out how many instances would be generated seems a little unnecessary.

Although, I have a feeling Verilator unrolls the generate statements anyway, so using the Verilator XML solves this issue for free 👍