Add variable space between module name and instance name

LiamSkirrow / verilogtree

Print out the modular hierarchy of a Verilog design

MIT License

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Open LiamSkirrow opened 1 year ago

LiamSkirrow commented 1 year ago

Include an option to specify the number of spaces between the module name and instance name, for example:

--space 1 (which is the default)

Control_Unit
├── Register_File u_reg_file_inst
└── alu u_alu_inst

and --space 4

Control_Unit
├── Register_File    u_reg_file_inst
└── alu    u_alu_inst