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LiamSkirrow / verilogtree

Print out the modular hierarchy of a Verilog design
MIT License
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Formatting of instance name print out #36

Open LiamSkirrow opened 1 year ago

LiamSkirrow commented 1 year ago

The printing of the instance name as well as the module name can get quite cluttered, so it's worth having some formatting options that help with readability.

Include the option to give characters separating the two items, for example

├── Register_File: u_reg_file_inst
---
├── Register_File | u_reg_file_inst
--- 
├── Register_File -> u_reg_file_inst
--- 
├── Register_File -> u_reg_file_inst
etc...

This should be combined with the option to select from (or let the user create their own, accept any symbol they enter) a set of enclosing characters for the instance name, for example:

├── Register_File  (u_reg_file_inst)
---
├── Register_File <u_reg_file_inst>
---
├── Register_File [u_reg_file_inst]
etc...

Also allow for a variable space between the enclosing character and the instance name, for example:

---
├── Register_File < u_reg_file_inst >
---
├── Register_File <   u_reg_file_inst   >
etc...

All of these parameters should have reasonable defaults and should be configurable in the .verilogtreerc file