LiamSkirrow / verilogtree

Print out the modular hierarchy of a Verilog design
MIT License
0 stars 0 forks source link

Include argument to set root node #45

Closed LiamSkirrow closed 11 months ago

LiamSkirrow commented 1 year ago

There should be a way to specify a known module in the design as the root node, such that this module is treated as the starting point. For example, for a given hierarchy like so:

altTop
└── mod2  
    └── mod1  
        └── mod3  
            └── mod4

Running verilogtree -f rtl/simple/*v -top mod1 should give:

mod1
└── mod3  
    └── mod4  
LiamSkirrow commented 11 months ago

This would also be useful just for general everyday use. If you want to print out a hierarchy but you don't know specifically which files to include to generate the hierarchy, you could simply just do a find . -name *.v and chuck that into verilogtree, then just specify the top level module you want to look at and verilogtree won't print out all the irrelevant modules.

LiamSkirrow commented 11 months ago

This ticket is almost complete, but I'd like to add some text down the bottom for specified top-level modules, to remind the user that the hierarchy they're viewing is modified and may not include all the modules in the design... Something like: "Using user-specified top-level modules: mod0 mod1 mod2" etc

LiamSkirrow commented 11 months ago

Should also create an example for this argument in the man page. Ex: verilogtree -f $(find . -name *.v -printf '%p ') --no-inst-name --top mod0 mod1

mod0
├── mod3  
│   └── mod4  
└── mod1  
    └── mod3  
        └── mod4  

mod1
└── mod3  
    └── mod4