Falsely detecting module instantiation on 'else if('

LiamSkirrow / verilogtree

Print out the modular hierarchy of a Verilog design

MIT License

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Open LiamSkirrow opened 10 months ago

LiamSkirrow commented 10 months ago

Funnily enough, else if( causes a false triggering of the module instantiation parsing. Need to create an edge case for this, possibly hardcoded...