Compile times are getting insane with 16GB RAM. Split out several shared libs of either modules, or object families (as Teigha does). With modules encode/decode split compile-time will still require >10min, only with the dwg.spec splitup it will become managable. so split out dynblocks and maybe acsh solids, surfaces
Compile times are getting insane with 16GB RAM. Split out several shared libs of either modules, or object families (as Teigha does). With modules encode/decode split compile-time will still require >10min, only with the dwg.spec splitup it will become managable. so split out dynblocks and maybe acsh solids, surfaces
or maybe just upgrade to 32GB RAM (160EUR)