LS_DRV and Q2 interaction

[X-Ryl669]

I'm wondering why Q2 gate is connected to LS_DRV signal. I'd have understood if it was connected to a STM32 GPIO as a way to prevent current flowing in reverse from the battery to the solar panel.

In the current schematic, in normal operating conditions, wouldn't Q2 enable/disable with LS_DRV, thus preventing some current to flow from the solar panel when "charging" the inductor and, as such, reducing the efficiency of the DC/DC buck stage and reducing Q2 life expectancy ?

[martinjaeger]

The trick is that the gate of Q2 (with its parasitic capacitance) is discharged through the weak 1MOhm pull-down only and discharging takes longer than one switching period. This means while the half bridge driver is switching, the gate of Q2 is continuously topped up and thus stays on all the time. The diode D1 is necessary to prevent it from being discharged by the MOSFET driver together with Q4.

[X-Ryl669]

But... When you have a low duty cycle, for example, at dawn when the sun is low and the solar panel voltage is close (but above) to the battery voltage, Q4 must be off else it'll burn (since if it's on for too long, it's acting as a shortcut on the battery + voltage line to the ground).

In that case, nothing will charge Q2's parasitic capacitance and it'll stop conducting, won't it ? Then, since Q2 is isolating the gnd from the solar panel (-), the solar (+) line will be floating. Since the circuit is measuring the solar + voltage against the ground (not solar -), then the decision to enable Q2 will/might not happen until some time.

As soon as the voltage increase, Q1 will conduct less often and Q2 will be switched on and I understand your logic in that case.

[martinjaeger]

The duty cycle will never get to 100% as we need to supply the bootstrapping capacitor C10 to have sufficient driving voltage for the high-side MOSFET. So Q4 will also never be turned off completely.

This is a synchronous buck topology, so at very low average currents the inductor current waveform can even get below zero for short periods of time.

[X-Ryl669]

The main issue is when Q4 is turned on completely (or close to completely). In that case, it can burn, since the battery will shortcut into it directly. And this happens when the duty cycle is close to 0, IIUC.

In many of not most synchronous buck topology I know about, this is avoided by turning both Q1 and Q4 off at the same time when the duty cycle is 0-ish (threshold to be defined). Then, if Q1 and Q4 are off, Q2 will be off too and I don't see how it can bootstrap to on again later on, since you need to turn Q4 on to be able to read a meaningful solar panel voltage (that is, between solar + and solar - minus voltage drop in Rds of Q2).

[martinjaeger]

The duty cycle is defined as follows:

D = t_HS,on / (t_HS,on + t_HS,off) = V_out / V_in

It can never go towards 0 (prevented by firmware), as this would mean that the input voltage goes towards infinity (given a fixed battery output voltage).

See also DC/DC converter on learn.libre.solar.

[X-Ryl669]

Right. This is the theoretical ratio, but the real ratio is less obvious.

Since Q4 will need at least 5V for the PSMN5R2 to commute, there's a minimum duty cycle where it'll not actually commute in saturation mode and instead, work more or less in linear mode. When this happens, the inductor current will flow in the MOSFET and so will the battery current, with a DC Vout voltage (and not the lower saturated Vds gate voltage).

Depending on the "on" time, so the actual duty cycle for this transistor, it means that you'll have a huge power consumption/dissipation on the drain/source of the MOSFET with 12V on its Rds. That's the main reason why those transistors are frequently blown up on the synchronous buck designs.

With typical numbers, if you have Vin at 80V and Vout at 12V (nominal), it means that a duty cycle of less than 15% will actually turn Q4 always on and in that case, you'll have 12V on a equivalent resistance of Rds + 3mOhm + inductor parasitic resistance (let's say 1 ohm total), so a power to dissipate of 144W*15% ~= 22W in the MOSFET.

To avoid this, when the duty cycle is below some threshold computed from the MOSFET maximum allowed power dissipation with a margin (and the actual measured Vout value), the main idea is to switch off both MOSFET (Q4 and Q1 in that case), which isolate Vin from Vout instead. If you don't do this, I wonder you'll have a lot of Q4 to replace in real life usage of the circuit.

Else if you do this, Q2 will, later, isolate solar (-) from the ground and that's my issue in understanding your circuit.

[martinjaeger]

I'm not sure if I understand correctly what you mean, but it's an interesting discussion!

So let's assume that the battery voltage is always above 10V, otherwise we don't start the DC/DC. In this case our MOSFET driver supply voltage is slightly less than the 10V, but still enough to turn the PSMN5R2 (logic-level MOSFET) fully on. The MOSFET will be in the linear region only for a couple of nanoseconds per switching cycle during turn-on and turn-off, but not 15% of the time. And the switching losses will be the same independent of the duty cycle.

Turning both MOSFETs Q4 and Q1 off at the same time means we turn off the entire DC/DC converter. So why would we want to do that while there is still solar power available?

[X-Ryl669]

I'm reading the code right now and it's well written so it's easy to follow. If I understand correctly, you set the minimum duty cycle from this line:

    half_bridge_init(DT_PROP(DT_INST(0, half_bridge), frequency) / 1000,
        DT_PROP(DT_INST(0, half_bridge), deadtime), 12 / hs_voltage_max, 0.97);

So the minimum value is a dynamic property (good!)

However, I don't see when you are disabling the timer for the PWM signal generation, so it would mean that you'd set a duty cycle to the minimum value and that's it.

[martinjaeger]

However, I don't see when you are disabling the timer for the PWM signal generation, so it would mean that you'd set a duty cycle to the minimum value and that's it.

It is stopped in the Dcdc::control() function (can be for various reasons like low power, too high voltage, manually stopped).

[X-Ryl669]

Right (sorry, posting answer in FIFO order). I'm not saying that Q4 is in the linear region 15% of the time. It's in the saturation region ~85% of the time if the duty cycle is 15% (well, except for the negligible time where both Q1 and Q4 are off to avoid half bridge shortcut). The mosfet driver circuit takes 15ns of rise time (from TI's datasheet), so I'd say that the linear region is small, 30ns per cycle, yet I don't know the PWM frequency to compute the actual linear region ratio. I assume it's peanuts. Yet in the linear region it'll consume like crazy. I'm not speaking of this consumption to explain the danger. I'm speaking of the 12V on Q4's drain over a 1 ohm resistor (so 12A) in the saturation region.

In the example above however, you have the solar panel producing 0A at 80V (typical Voc) and a battery at 12V. You want Vout = 12V so technically, switching off the DC/DC is the best move to do, efficiency wise. If you don't, the duty cycle will turn on Q4 85% of the time (Duty = 0.15), and when it's doing that, the battery current will flow in Q4 since it's a shortcut to the ground, heating it up. You want 0A to flow in the battery (and obviously, you don't want the battery to act a source).

In the 15% of the time Q1 is on and Q4 is off, the solar panel is "forced in production", and a current will flow from the solar panel to the inductor & capacitor. Slowly lowering the panel voltage and increasing the current from the panel, increasing the duty cycle, yet, this will actually take a lot of time and while the MPPT is converging, you'll still heat the Q4 mosfet like crazy, until it burns or you finally reach a duty cycle where it's safe.

In a synchronous buck design, the lower the duty cycle, the longer Q4 is on and the inductor then doesn't act anymore as an inductor but as a wire. Thus, the battery voltage appears more or less on Q4's drain, with a very small resistance in this circuit => magic smoke. If it were an asynchronous buck, the diode (replacing Q4) would not conduct and Q1 would not burn. That's the downside of synchronous buck, don't let Q4 conduct for too long.

[X-Ryl669]

This example above is what happens when the battery is charged and you want 0A to go into the battery. In that case, still running the PWM seems like a dangerous action IMHO.

[martinjaeger]

In a synchronous buck design, the lower the duty cycle, the longer Q4 is on and the inductor then doesn't act anymore as an inductor but as a wire. Thus, the battery voltage appears more or less on Q4's drain, with a very small resistance in this circuit => magic smoke.

The inductor works in both directions, so it will also limit current flow from the battery through Q4 (low-side MOSFET) until it goes into saturation. Of course you need to make sure that the inductor does not saturate. But in order to saturate at 0A average current, the ripple current would have to be much more than the maximum average current the inductor was designed for. If that is the case, the inductor layout is just wrong.

[X-Ryl669]

Well, that's where you overlook it in my opinion. When the consign is 0A, and the duty cycle is low, the actual current in the inductor / Q4 is much much larger than 0A, since it's a basic ohm law going on here: the battery is shortcut by the inductor and Q4. You have this exact schematic in that case:

   .___/\/\/\/\___ + 12V
   |
  Q4            
   |
  GND            GND 

Thus the only thing limiting the current is the inductor's resistance (we can assume the Q4's Rds is negligible and the shunt resistor too), so you'll have a direct shortcut. In that case, if the resistance of the inductor is 1 Ohm (don't know it, but it's low), then you have 12A in Q4, not 0A.

Please notice that the voltage measure in the shunt resistor will tell you this, but since your consign is 0A and the duty cycle is only computed from the voltage ratio, there is nothing you can do to decrease it even more. The only solution is to open Q4 and Q1.

[martinjaeger]

Thus the only thing limiting the current is the inductor's resistance (we can assume the Q4's Rds is negligible and the shunt resistor too), so you'll have a direct shortcut. In that case, if the resistance of the inductor is 1 Ohm (don't know it, but it's low), then you have 12A in Q4, not 0A.

No, the thing limiting the current is the inductance! It's an inductor and not a resistor. We are switching at 50 kHz and the switch node (drain of Q4) is still alternating between Vin (e.g. 80V) and GND (neglecting the Rdson). The Ohmic resistance of the inductor is only around 5 mOhm, btw.

You'll probably have to come up with an LT-Spice simulation to convince me. I doubt you'll see any dangerous currents in Q4 under realistic operating conditions of the MPPT.

[X-Ryl669]

Ok, here are they: Current in Q4 DS: Voltage in the Q4 D: Power in Q4: (I think it averages to ~2W)

Circuit:

Used characteristics of the inductor from the datasheet, that is 47uF 15mOhm. Could not set the characteristic of the MOSFET exactly. V5 strange formula is to create a 0.85 duty cycle running at 70kHz (as you can see in VPWM)

[X-Ryl669]

For example here, if the duty cycle is 0.95, (so a D at 5% in the Buck design), the average power to dissipate increases to 10W:

[X-Ryl669]

Adding a 1nF capacitor on Q4 DS like in the schematic does not change anything to the results. Clearly, switching off the PWM is the best action here, power wise.

[martinjaeger]

Thanks for providing the images. However, the circuit is not a synchronous buck converter. The high-side MOSFET is missing (which will also provide a path for the inductor current if Q4 is open). That's also why we see these crazy high voltage spikes.

[X-Ryl669]

Nope, it only provide a path for the current if the solar panel is sinking them, but solar panels have a diode preventing current to flow backward. So when you Q1 is on, the current can't flow in the solar panel. It would even add to the issue since the solar panel current will flow to charge the inductor.

[X-Ryl669]

BTW, I've used circuitlab to simulate, but I'm running out of the trial limited time. Feel free to copy the circuit on your simulator to see by yourself. Ideally, you can simulate the whole circuit better with microcap software since it account for heat simulation and burning components analysis. The issue I'm describing is well know for sync buck design. See step 7 here. See here too

[martinjaeger]

Nope, it only provide a path for the current if the solar panel is sinking them, but solar panels have a diode preventing current to flow backward. So when you Q1 is on, the current can't flow in the solar panel. It would even add to the issue since the solar panel current will flow to charge the inductor.

But we have bulk electrolytic capacitors at the input of the DC/DC converter which will receive the current, so the energy is essentially continuously swapped between input and output capacitor at 0A average current.

[X-Ryl669]

And even here on your repository

[X-Ryl669]

Electrolytic capacitor will be charged in the 80V 0A mode and there's nothing to discharge them, so no, they won't sink the current.

[martinjaeger]

It's a bit funny that you insist that the circuit does not work and that it would burn low-side MOSFETs even though it is actually working since years in several different applications.

I don't know what's wrong with the designs on Instructables. I suspect it's a firmware issue (e.g. control algorithm bug) or a not well matched dead-time, which is software-configurable in the Libre Solar designs, but fixed if you use an IR2104.

[X-Ryl669]

My initial remark was, if you turn off Q4 and Q1, then how Q2 is controlled. If you don't turn off Q4 & Q1 like all other people do to avoid burning the Q4 mosfet, then Q2 is controlled and all is fine.

I think I've proved above that turning off the PWM is the best action efficiency-wise when reaching low duty cycle (instead of running the circuit with such low duty and heating the mosfet).

I think I've proved that in that situation Q4 is heating up and is more likely to burn. If it actually does not burn, well, congratulations, you're correctly cooling it down or you are in the out of spec range but you don't see it because you only have too few instance of the board.

But turning off the PWM would have even avoided this requirement and increased the efficiency in the longest usage time (since in most case, once you've maximized your battery charge, the circuit will run in low duty mode for as long as you don't draw load's current from the system). With a PWM off, the battery drain current is essentially 0, the voltage on the battery is constant and good, the solar current is 0. It's crazy to switch the transistors at 70kHz not to move any electron and just convert them to heat.

A bad dead time controlling Q1 and Q4 would burn both MOSFET when they are both conducting. The links I've posted above clearly show that only Q4 was burning. So it's not a bad dead time (and the IC they use is used in thousand of applications, I doubt it's not working).

They also come to the same conclusion as I did, that a low duty cycle is damaging the efficiency and also the low side mosfet, that's why they actually propose to turn off the PWM to avoid this (and it works for them).

[martinjaeger]

My initial remark was, if you turn off Q4 and Q1, then how Q2 is controlled. If you don't turn off Q4 & Q1 like all other people do to avoid burning the Q4 mosfet, then Q2 is controlled and all is fine.

"All other people" being those two people on Instructables?

I think I've proved above that turning off the PWM is the best action efficiency-wise when reaching low duty cycle (instead of running the circuit with such low duty and heating the mosfet).

No. Turning the MOSFETs off as soon as the average current towards the battery gets negative is the best action for best efficiency. If you can't measure currents around 0A or in negative direction, this approach might be difficult, though. In that case you might have to turn off based on duty cycle thresholds.

I think I've proved that in that situation Q4 is heating up and is more likely to burn.

No. You have simulated a circuit that is completely different from the actual circuit of this MPPT.

But turning off the PWM would have even avoided this requirement and increased the efficiency in the longest usage time (since in most case, once you've maximized your battery charge, the circuit will run in low duty mode for as long as you don't draw load's current from the system). With a PWM off, the battery drain current is essentially 0, the voltage on the battery is constant and good, the solar current is 0. It's crazy to switch the transistors at 70kHz not to move any electron and just convert them to heat.

Maybe there was a misunderstanding. The PWM will eventually be switched off, but only as soon as no current goes into the battery anymore. As long as there is still a little bit of power coming from the solar panel, low efficiency is still better than 0% efficiency (PWM off, no power flow).

[X-Ryl669]

Sorry, I missed your answer... My bad.

The PWM will eventually be switched off, but only as soon as no current goes into the battery anymore. As long as there is still a little bit of power coming from the solar panel, low efficiency is still better than 0% efficiency (PWM off, no power flow).

Ok, that's what I asked initially. The situation I was describing was exactly this, static full charged battery. In that case, the PWM will be off and that's ok (and expected).

The threshold from where to turn off the PWM is when the "available" energy from the solar panel is just above the energy lost in the Q4/Q1/inductor tuple. Ideally, this threshold should be high enough not to run the mosfet in their "heat up / low efficiency" region to avoid premature fatigue.

I've seen it's dynamic in the code, and I was wondering where it's set and you've answered.

How it's computed, I don't know, but I guess it's possible to measure it with an amp meter and figure out what is the best value and take some margin. Maybe you have a simulation of the whole circuit and it can be set up from here ?

Using the parasitic capacitance of Q2 (thus not in the schematic and probably variable between each board/chip) was what I failed to see. Maybe it would be better to have a very small (pF) capacitor on the schematic ?