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Lightelligence / rules_verilog

Bazel build rules for compiling Verilog
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Converted verilog_dv_test_cfg to output everything in *_dynamic_args #18

Closed ciglass closed 2 years ago

ciglass commented 2 years ago

Converted verilog_dv_test_cfg to output everything in _dynamic_args.py instead of splitting between _dynamic_args.py and _sim_args.f