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Lightelligence / rules_verilog

Bazel build rules for compiling Verilog
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Integrate the VCS flow #29

Closed justin371 closed 1 year ago

justin371 commented 1 year ago

Integrate the VCS flow based on the latest commit number

ciglass commented 1 year ago

I read through the simmer code and these rules_verilog changes again, and I think it should be straightforward to merge the flists in the rule implementations. The per-vendor templates you've made are good, but I think we should instead use a new argument on verilog_dv_library and verilog_dv_tb that determines if we render from Synopsys or Cadence vendor templates. If we only render a single set of templates (instead of one per vendor) then the simmer code is simpler as well.

justin371 commented 1 year ago

2 groups of filelists is more clear for the different simulators, and maybe more efficient for the maintainance, will not be impact on other filelist, only more filelists are created in the bazel-bin path.

justin371 commented 1 year ago

Currently only 2 simulators are enough for us, and more filelists are created only. Furthermore, The compilation and simulation results are different between the VCS and Xcelium, so the plan is to run both VCS and Xcelium in CN side.

justin371 commented 1 year ago

one more words, it seems the "-makelib/-reflib" is a better approch: image