Fix IO 32-bit limit, adjust JNB accordingly, JNB improvements

Logicademy / PYNQ-SoC-Builder

This project automates process of creating a PYNQ Z1/Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.

GNU Affero General Public License v3.0

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Fix IO 32-bit limit, adjust JNB accordingly, JNB improvements #17

Closed lukecanny closed 8 months ago

lukecanny commented 8 months ago

In this pull request:

New procedures added to generate_procs.tcl file (add_slice_ip, add_concat_ip)
Support for >32 bit buses, there is an assumption that only HEX will be used for these larger signals.
Interconnect and connection automation actions updated to support added GPIO
JNB now has summary of each test case in each test cell
Hex and binary values are padded