Verilog Support - Githubissues

Logicademy / PYNQ-SoC-Builder

This project automates process of creating a PYNQ Z1/Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.

GNU Affero General Public License v3.0

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Verilog Support #20

Closed lukecanny closed 8 months ago

lukecanny commented 8 months ago

Verilog projects now working with new HDL Wrapper Tcl API in generate_procs.tcl file