This project automates process of creating a PYNQ Z1/Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.
Implemented ability to check for clk signal and handle delays.
Based on the following format regardless if clock signal exists or not (delay is there regardless)
Signals RWr rd rs1 rs2 rs1D rs2D WBDat ce Delay TestNo Note
Mode in in in in out out in in None None None
Radix 1'b 5'h 5'h 5'h 32'h 32'h 32'h 1'b None None None
= = = = = = = = = = = =
0 00 00 00 00000000 00000000 00000000 0 1 1 Note for test number 1
0 00 00 00 00000000 00000000 00000000 0 1 2 Note for test number 2
0 00 00 00 00000000 00000000 00000000 0 1 3 Note for test number 3
# Example of a comment - comments are ignored by the testplan generator
Can handle both txt and html-encoded formats as far as I understand.
Implemented ability to check for clk signal and handle delays. Based on the following format regardless if clock signal exists or not (delay is there regardless)
Can handle both txt and html-encoded formats as far as I understand.