Lora-net / sx1302_hal

SX1302/SX1303 Hardware Abstraction Layer and Tools (packet forwarder...)
Other
219 stars 271 forks source link

why in version sx1302_hal 2.1.0 not compile test_loragw_spi? #102

Closed techsd closed 8 months ago

techsd commented 1 year ago

why in version sx1302_hal 2.1.0 not compile test_loragw_spi?

mcoracin commented 1 year ago

test_loragw_spi has been replaced by test_loragw_com which allows to test direct sx1302 register access trough SPI, or through USB.

techsd commented 1 year ago

ok why when i use "chip_id -u -d /dev/ttyAMA0" i have "Opening USB communication interface INFO: Configuring TTY INFO: Flushing TTY INFO: Setting TTY in blocking mode INFO: Connect to MCU ERROR: received wrong ACK type (0x00) ERROR: failed to read PING ack ERROR: failed to ping the concentrator MCU ERROR: failed to start the gateway"

but when i use USB - microUSB patchcord and use "chip_id -u -d /dev/ttyACM0" i have Opening USB communication interface INFO: Configuring TTY INFO: Flushing TTY INFO: Setting TTY in blocking mode INFO: Connect to MCU INFO: Concentrator MCU version is V01.00.00 INFO: MCU status: sys_time:713307 temperature:23.8oC Note: chip version is 0x10 (v1.0) INFO: using legacy timestamp ARB: dual demodulation disabled for all SF INFO: concentrator EUI: 0x0016c001f153a19e Closing USB communication interface

It turns out that the SPI does not work or the configuration in the file reset_lgw.sh is not correct

techsd commented 1 year ago

when i run test_loragw_com i have CoreCell reset through GPIO23... SX1261 reset through GPIO23... CoreCell power enable through GPIO18... CoreCell ADC reset through GPIO13... Beginning of test for loragw_com.c Opening SPI communication interface SX1302 version: 0x00 Cycle 0> error during the buffer comparison Written values: BB 1E 56 19 D1 5A 46 E8 A2 DE 7E CB B8 E9 62 D9 Read values: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Closing SPI communication interface End of test for loragw_com.c

techsd commented 1 year ago

when use "chip_id -d /dev/spidev0.0" i have CoreCell reset through GPIO23... SX1261 reset through GPIO23... CoreCell power enable through GPIO18... CoreCell ADC reset through GPIO13... Opening SPI communication interface Note: chip version is 0x00 (v0.0) ERROR: Failed to set SX1250_0 in STANDBY_RC mode ERROR: failed to setup radio 0 ERROR: failed to start the gateway

I don't know where to dig yet

RoyceThomasIype commented 1 year ago

I'm also facing the same issue. Did you find a solution?

techsd commented 1 year ago

in source need finde #define COM_PATH_DEFAULT "/dev/spidev0.0" modify to "/dev/ttyACM0"

mcoracin commented 1 year ago

If you use a USB corecell, you need to use the option "-u -d /dev/ttyACMx". No need to run the reset_lgw.sh script.

If you are using an SPI corecell, you need to use the option "-d /dev/spidev0.0", and it is required to run the reset_lgw.sh script before any too usage.

There is nothing to modify in the source code, just use the proper options, with the proper board.

Best regards

RoyceThomasIype commented 1 year ago

I'm using an SPI corecell. I'm still getting the same error:

ERROR: Failed to set SX1250_0 in STANDBY_RC mode ERROR: failed to setup radio 0 ERROR: failed to start the gateway

mcoracin commented 1 year ago

Which board is it (corecell and host board) ? The reset_lgw.sh controls some GPIOs, which depends on how it is connected to your host board.

RoyceThomasIype commented 1 year ago

Which board is it (corecell and host board) ? The reset_lgw.sh controls some GPIOs, which depends on how it is connected to your host board.

The host is a Raspberry Pi3B, and the corecell is SX1302.

mcoracin commented 1 year ago

How both are connected together ? Is it in line with the GPIOs toggled by the reset_lgw.sh script ?

RoyceThomasIype commented 1 year ago

I am using a custom interface board. The issue was with the GPIO pin mappings in the reset_lgw.sh script. I modified the pin mappings and it works fine. Thanks for the help!