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LudwigCRON
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reflow
Analog/Digital/Mixed Signal Simulation Flow
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create a spice netlist and a symbol of digital bloc
#1
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LudwigCRON
opened
4 years ago
LudwigCRON
commented
4 years ago
From a verilog module:
synthesis of the module -> spice netlist
create symbol for ltspice/cadence -> mix mode simulation
From a verilog module: