verilog generation

[LudwigCRON]

proposition of enhancement:

From the given input file, the tool can generate a verilog sequence for simulation purpose. This could save time to the designer and ensure it respect the specification.

this need a new inputs from the designer such as:

• tick period: 20 (equal to #20 ; in verilog for a given timescale)
• list of signal to be generated
• list of signal to be asserted

[LudwigCRON]

Propose to generate a generator/checker verilog module as the following

module name_of_the_input_file #(
    // scale factor to adjust the timing of the dut
    parameter realtime TICK_PERIOD = 100ns
) (
    inout wire signal_name,
    // while 1 generate signal_name
    input wire gen_signal_name,
    // while 1 check signal_name
    input wire chk_signal_name,
    ...
);

...
wire new_op_signal_name;
assign new_op_signal_name = gen_signal_name | chk_signal_name;

task gen_chk_signal_name();
...
endtask

always @(posedge new_op_signal_name)
        gen_chk_signal_name();
...

endmodule

The module shall count the number of errors and display on which signal it occurs and at which moment.

• [ ] input file name reformat
• [ ] task able to generate and check signal
• [ ] ignore check if 'x'
• [ ] detect width of signal
  • wire if z01xhlnpHLNP only
  • bus if =2345 and widest data set the width
  • real if asc
• [ ] generate unsupported field error for unsupported bricks
• [ ] transform svg path into list of floats
  • apply thresholds for 01Z
  • detect X symbol
  • no threshold if analog but scale to VDDA and VSSA
• [ ] add input real VDDA to verilog if analog detected
• [ ] add input real VSSA to verilog if analog detected