The design needs to be extended with a data memory (separate from the instruction memory) such that LDR and STR can load / store to memory.
For simplicity assume that the LDR and STR are word aligned.
Beware that loading from the same address following a STR should give the new value.
Need to implement the basic LDR and STR instructions. LDR 0 1 0 1 1 0 0 Rm Rn Rt Rt = [Rn + Rm] STR 0 1 0 1 0 0 0 Rm Rn Rt [Rm+Rn] = Rt LDR 0 1 1 0 1 Imm5 Rm Rd
STR 0 1 1 0 0 Imm5 Rn Rt
The design needs to be extended with a data memory (separate from the instruction memory) such that LDR and STR can load / store to memory. For simplicity assume that the LDR and STR are word aligned. Beware that loading from the same address following a STR should give the new value.