DDR RX glitches - Githubissues

M17-Project / OpenHT-fpga

OpenHT FPGA design

GNU General Public License v3.0

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Closed sp5wwp closed 1 year ago

sp5wwp commented 1 year ago

zero_word signal that's supposed to run at 400 kHz, sometimes glitches. Cranking up the clk_152 to just above 170 MHz helps.

sp5wwp commented 1 year ago

Nonexistent with current setup.