Core: cleanup all Vivado warnings and timing violations

[lydon42]

Currently a syntax check will fail because we have lots unclean VHDL.

• [ ] cleanup code to get a check-MODEL run without producing CRITICAL messages
• [ ] help Vivado to not produce timing violations

[lydon42]

Current state of the syntax check in development:

./vivado_check mega65r3
CRITICAL WARNING: [HDL 9-3134] 'mega65r5_board_i2c' is not compiled in library 'xil_defaultlib' [/home/ograf/devel/mega65/m65c-dev/src/vhdl/iomapper.vhdl:1421]
CRITICAL WARNING: [HDL 9-1314] Formal port/generic <write_n> is not declared in <cpu6502> [/home/ograf/devel/mega65/m65c-dev/src/vhdl/internal1541.vhdl:276]
CRITICAL WARNING: [HDL 9-3500] formal port 'data_i' has no actual or default value [/home/ograf/devel/mega65/m65c-dev/src/vhdl/internal1541.vhdl:270]

CRITICAL WARNING: [HDL 9-1314] Formal port/generic <write_n> is not declared in <cpu6502> [/home/ograf/devel/mega65/m65c-dev/src/vhdl/internal1541.vhdl:276]
CRITICAL WARNING: [HDL 9-3500] formal port 'data_i' has no actual or default value [/home/ograf/devel/mega65/m65c-dev/src/vhdl/internal1541.vhdl:270]