MEGA65 / mega65-core

MEGA65 FPGA core
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fix mix-up of two rx eth frames when buffers are full #653

Closed ki-bo closed 1 year ago

ki-bo commented 1 year ago

There is the eth_rx_blocked_50mhz signal preventing that new bytes received are written to the buffers in case all rx buffers are full. If in the middle of such an "ignored" packet the CPU frees up one more buffer then that signal is set immediately, and the state machine continues writing bytes into the now free buffer. This leads to a buffer containing partly old and partly new data, thus garbage. The CRC32 is not detecting this because it is not applied on the rx buffer bytes but on the bits received from the transceiver.