MEGA65 / mega65-core

MEGA65 FPGA core
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Sometimes ADC/SBC mis-behaviour after eth tx trigger #696

Closed ki-bo closed 1 year ago

ki-bo commented 1 year ago

Test Environment (required) You can use MEGA65INFO to retrieve this.

Describe the bug When doing adc/sbc operations after an ethernet packet TX trigger (putting 1 into $d6e4), then the result seems to be wrong sometimes. That means, this bug is triggered by the TX send command, but not reproducible 100%, there is some probability.

To Reproduce Steps to reproduce the behavior:

  1. Use the attached prg and run it
  2. It will do TX trigger in a loop and then does a sequence of SBC operations with two constants and checking the result
  3. If a wrong result is detected, the program will halt with a yellow screen background color

Expected behavior The screen shall never turn yellow even after long times of running the program

ethbug.prg.gz