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MEGA65 FPGA core
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VIC-III errata level register #731

Closed dansanderson closed 1 month ago

dansanderson commented 10 months ago

We currently offer VIC-III bug fixes that cause backwards compatibility issues with early MEGA65 software behind a register flag that is off by default: D07A.5. New software can enable the flag to get all the fixes; old software doesn't know about it and runs with old behavior that otherwise matches the C65 prototype. This has the problem that software written between two bug fixes may need old fixes enabled and new fixes disabled.

Based on SteerCo conversations, we think it might be better for an 8-bit register at $D08F to represent the "errata level," where each set of fixes is assigned to a new level. We don't expect to need more than 256 levels in the history of the project. This level is $00 at the boot state, so software will need to opt in to whatever level it is known to be compatible with, and won't be affected by future fixes.

dansanderson commented 5 months ago

This is fixed in v0.96. I don't know how we want to tag or manage the issue while the release is in progress.