And Gardners suggested it could be possible to save additional cycles :
Question :
with this improvement, these "empty" chars are not needed anymore isn't it ?
Gardners Answer :
Correct!
it means you need to tell RRB to mask the rows (which means some extra RRB tokens), but you save 64 bytes per soft sprite column,
and probably some RRB cycles during the painting.
Because if we want to draw only that one row in my last example above, we could now say "paint only row 7 of the next char", and then display the char.
The VIC-IV will then only draw that row.
**It's also possible that I was clever and made row masking skip even reading the bytes from chip RAM for the row,
but I'm not sure. each pixel costs 1 VIC-IV cycle to paint. ie one 81MHz tick.
Just confirmed you still pay the cycles during fetch of a masked row.and the pixel painting.
It literally just pretends to have read $00 from the chip RAM So sad. But that's how it is right now.
It means right now that there is no RRB cycle saving from using the row mask.
Just the bytes of chip RAM saved, because you don't need the blank rows any more.
Yes, it can be optimised to save at least 8 RRB cycles per blank row, potentially 16, if I could do it on both the fetch and paint stages.**
We had a discussion on Discord regarding the following RRB improvement :
https://github.com/MEGA65/mega65-core/issues/340 "Allow masking of each pixel row to allow for more flexible RRB Y scrolling"
And Gardners suggested it could be possible to save additional cycles :
Question :
with this improvement, these "empty" chars are not needed anymore isn't it ?
Gardners Answer :
Correct!
it means you need to tell RRB to mask the rows (which means some extra RRB tokens), but you save 64 bytes per soft sprite column, and probably some RRB cycles during the painting.
Because if we want to draw only that one row in my last example above, we could now say "paint only row 7 of the next char", and then display the char.
The VIC-IV will then only draw that row.
**It's also possible that I was clever and made row masking skip even reading the bytes from chip RAM for the row, but I'm not sure. each pixel costs 1 VIC-IV cycle to paint. ie one 81MHz tick.
Just confirmed you still pay the cycles during fetch of a masked row.and the pixel painting. It literally just pretends to have read $00 from the chip RAM So sad. But that's how it is right now.
It means right now that there is no RRB cycle saving from using the row mask. Just the bytes of chip RAM saved, because you don't need the blank rows any more.
Yes, it can be optimised to save at least 8 RRB cycles per blank row, potentially 16, if I could do it on both the fetch and paint stages.**