R3A and later boards have 8MB of QSPI Flash, which is subdivided into 8 slots of 8 MB each. A current r3/r4 core takes up just over 6 MB of space, so there is not much left.
But the C64 Core is only 4.4 MB and the Arcade cores are just below 4 MB (something like 3.6), so it would be possible to put two cores of that kind into one core slot.
We could either allow MEGAFLASH the combination of two core files into one, or this could be a bit2core option. Either way, there needs to be a special header field that has a pointer to the start of the second core (or even a third chained?). It would be better to leave the combination feature out of the MEGAFLASH code, as it might use up to mach spaces, but bit2core is a great candidate.
Either way MEGAFLASH needs to be able to recognize this, display the second (or even third?) core name/version, and allow the user to select it in some way (ALT-NUM?).
R3A and later boards have 8MB of QSPI Flash, which is subdivided into 8 slots of 8 MB each. A current r3/r4 core takes up just over 6 MB of space, so there is not much left.
But the C64 Core is only 4.4 MB and the Arcade cores are just below 4 MB (something like 3.6), so it would be possible to put two cores of that kind into one core slot.
We could either allow MEGAFLASH the combination of two core files into one, or this could be a bit2core option. Either way, there needs to be a special header field that has a pointer to the start of the second core (or even a third chained?). It would be better to leave the combination feature out of the MEGAFLASH code, as it might use up to mach spaces, but bit2core is a great candidate.
Either way MEGAFLASH needs to be able to recognize this, display the second (or even third?) core name/version, and allow the user to select it in some way (ALT-NUM?).