The /INT line that causes the FPGA to power on should be connected to the Xilinx FPGA. Trick is when VCC_FPGA is off, the /INT line will be floating, and we won't want back-current flowing into the FPGA. It might be possible to use the unused S-R flip-flop of the 74HC74 to achieve this. Or alternatively use a buffer with an /OE line that can be tied to /INT, so that it tri-states when /INT is high. That's probably the best option.
For the first prototype, where VCC_FPGA has to stay on to power the I2C IO expanders that control all other power sources we can probably just connect it directly. Or at worst with something like a 10K resistor, so that current flow is severely limited, but it will still be able to pull-down when /INT goes low for long enough.
The /INT line that causes the FPGA to power on should be connected to the Xilinx FPGA. Trick is when VCC_FPGA is off, the /INT line will be floating, and we won't want back-current flowing into the FPGA. It might be possible to use the unused S-R flip-flop of the 74HC74 to achieve this. Or alternatively use a buffer with an /OE line that can be tied to /INT, so that it tri-states when /INT is high. That's probably the best option.
For the first prototype, where VCC_FPGA has to stay on to power the I2C IO expanders that control all other power sources we can probably just connect it directly. Or at worst with something like a 10K resistor, so that current flow is severely limited, but it will still be able to pull-down when /INT goes low for long enough.