Open qasii21 opened 2 years ago
Sorry to respond this late. I think set should be triggered so that clock can start
Am I going to change it on the test bench?
Hello May I ask how to trigger the set? Do you have any documentation on your project? Please help me.thank you very much
On Tue, May 24, 2022, 2:12 PM MJVARMA, @.***> wrote:
Sorry to respond this late. I think set should be triggered so that clock can start
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Hey qasii I think you are including clockdivider and other seven segment controlling codes while simulating, you should comment those before behavioural simulation. Cuz its working fine for me.
My problem is about the digital alarm clock. The one you shared is a digital clock.
May I ask if you already implemented it on the FPGA board?
On Sat, May 28, 2022, 11:27 AM MJVARMA, @.***> wrote:
Hey qasii I think you are including clockdivider and other seven segment controlling codes while simulating, you should comment those before behavioural simulation. Cuz its working fine for me. [image: Screenshot from 2022-05-28 08-39-35.png] https://user-images.githubusercontent.com/47537344/170808112-69688375-173b-4317-a92e-05db1a3be8c4.png
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I implemented the code on the board and its working fine
I have different results with the behavioral simulation upon running your codes. Could you help me to fix it? thank you