MarcBoule
commented
4 years ago I'll think about this, but just so you know, the "100% percent right" you mention is technically not 100% since you have to be very unlucky to click reset while a 10ms trigger is high, but it is still possible and could happen. Clicking reset while a 50% duty cycle clock is high is 50% chance, but a 10ms trigger during a 0.5s interval (120 BPM), means 2%, which translates to 98% in your case above instead of 100% :-) Sorry to be all mathematical with this, but I just want you to know that it's not 100% even with triggers. And once this is establised, it can be bad to actually think it is 100% (during all practice runs) and then when we're finally performing the final take, we are unlucky and manage by accident to hit reset while the trigger happens to be high.
So if I understand, only CLKD would need this, since in Clocked we already have the pulse width control that can already do this.
vcvrackideas
Hi Marc!) I found a funny thing on how different resets\clock (gate vs trig) behave in Rack! When a clock module has gates on its outputs it becomes tricky to click on reset to get the right starting point of all modules that can receive clock\reset pair, I tested on BPM LFO and some step sequencers as well. While using trigger outputs makes 100 right behavior and I don't know why :-) How I found that? ZZC Clock has right click options to switch each of the 3 outputs to gates or trigger. And with gates choosen I got similar behavior that was with CLKD and with trigger there was all right while hitting reset button any time. So based on that experience I'd like to suggest you to add trigger\switch in right click menu to CLKD. Cheers!