Custom combinatorial components with Verilog.

[ms8817]

It would be nice to be able to define combinatorial components using a subset of Verilog.

Steps:

• [ ] Setup a text editor. The best way is to probably wrap the react-simple-code-editor and display in a popup like the memory editor.
• [ ] Write a parser for a Verilog combinatorial subset.
• [ ] Create a function to use the parsed Verilog as a reducer for a simulation graph node.
• [ ] Join everything together and test it.