MarcosYonamine963
commented
1 year ago Binary do Dice display Decoder
Here, we have the 3-bit binary inputs (Q0 ~ Q2) coming from the binary counter, and the LEDs outputs (a ~ g) at the dice display.
For each output, we have already solved the Karnaugh Maps, obtaining:
$$a = f = Q_0\cdot Q_1 + Q_2$$
$$b = e = Q_0 \cdot Q_2$$
$$c = d = Q_0 + Q_1 + Q_2$$
$$g = \overline{Q_0}$$
Using the logic gates AND (74LS08), OR (74LS32) and NOT (74LS04), the circuit is shown below:
Main Concept
Functional Diagram
First, an unstable clock is generated, and a push button enables the clock to the binary counter. The counter is configured to count from 0 to 5 (mod 6). Then, the 3-bit binary signals are decoded to a 7-LED Dice Layout display.
Unstable Latch Clock Generator and Push Button
The clock generator is based on the switching NAND gates (working as NOT gates) in loop. Observe that the frequency is based on the RC time constant.
The clock signal is sent to the Push Button, which doesn't need a debouncer, because the objective here is to generate an imprecise clock signal. In fact, the boucing signal at the button also improve the randomness of the generator.
3-Bit Binary Counter (mod 6)
Using 3 JK Flip-Flop, it's possible to implement a 3-bit binary counter. For that, it was used a 74LS93 4-bit binary counter, but used only the 3 first outputs. Also, the counter has the reset function, which was configured to reset on binary 6 (0xb110). Therefore, the counter goes from 0 to 5.
3-Bit binary to 7-LED Dice Display Decoder
The custom Dice Display is implemented with simple 7 leds (a ~ g), disposed as a Dice layout.
For 3 bits input, there are 8 possible combinations. The complete truth table of the inputs and desired outputs is shown below. Logic ones means LED ON, and logic zeros mean LED OFF.
Note that because the counter goes from 0 up to 5, the binaries 6 and 7 have the outputs as "X", interpreted as "doesn't matter", because that inputs are impossible. Those X can help to solve the Karnaugh Map, being interpreted as 0 or 1, depending on each neighbor bit.
Also, if you look and compare the outputs carefully column by column, you'll see that a = f, b = e and c = d. Only output g doesn't have a pair.
So, the circuit should have 4 outputs: a, b, c and g, and the others outputs will have the respective same behavior as it's pairs, simplifying the circuitry.
Now that the complete truth table of the desired output behavior is done, it's possible to project each output circuit using Karnaugh Map method. For that, it's needed to build 4 output maps (a, b, c and g).
If you are leaning Karnaugh Map method, do this exercise: build and solve the maps for all outputs and certify yourself the equivalent pairs.
Output a (and f) Karnaugh Map
$$ a = Q0 \cdot Q1 + Q2 $$
Output b (and e) Karnaugh Map
$$ b = Q0 \cdot Q2 $$
Output c (and d) Karnaugh Map
$$ c = Q0 + Q1 + Q2 $$
Output g Karnaugh Map
$$ g = \overline{Q0} $$