kernel mode : tlb

[Martins3]

• [x] kvm_vz_vcpu_load_tlb
• [ ] kvm_vz_vcpu_load_wired
  • [ ] why load tlb in kvm_vz_vcpu_run instead of everytime vmexit

TLB need special attention

1. should we copy TLB used in host to guest mode ?

   Copy code from tlb.c is error-prone

   • sharing global variable with mips kvm maybe disturb kvm

     We shouldn't remove request related code

   • [ ] vz:requests and remote tlb flush

     We shouldn't remove mode related code

   • [ ] vz_vcpu::mode , check it's corresponding code in the kvm and find all the code

[Martins3]

• [ ] set_root_gid_to_guest_gid

  /**
  * set_root_gid_to_guest_gid() - Set GuestCtl1.RID to match GuestCtl1.ID.
  *
  * Sets the root GuestID to match the current guest GuestID, for TLB operation
  * on the GPA->RPA mappings in the root TLB.
  *
  * The caller must be sure to disable HTW while the root GID is set, and
  * possibly longer if TLB registers are modified.
  */
  static inline void set_root_gid_to_guest_gid(void)

  :bug: sets the root GuestID to match current guest CuestID

[Martins3]

GuestID

• GuestCtl1_ID

• GuestCtl1_RID

  A system implementing a GuestID is required to support a guest identifier field (GID) in each Guest and Root TLB entry. This GuestID field within the TLB is not accessible to the Guest. While operating in guest context, the behavior of guest TLB operations is constrained by the GuestCtl1_ID field so that only guest TLB entries with a matching GID field are considered.

• GuestCtl0_RAD : RAD, or “Root ASID Dealias” mode determines the means that a Virtualized MMU implementation uses Root ASID to dealias different contexts.

  • 0 GuestID used to dealias both Guest and Root TLB entries.
  • 1 Root ASID is used to dealias Root TLB entries, while Guest TLB contains only one context at any given time.

• GuestCtl0_DRG : DRG, or “Direct Root to Guest” access determines whether an implementation provides root kernel the means to access guest entries directly in the Root TLB for access to guest memory. If GuestCtl0_DRG=1 then GuestCtl1_RID must be used. If GuestID for root operation is non-zero, root is in kernel mode, Root.StatusEXL,ERL=0 and DebugDM=0, then all root kernel data accesses are mapped, root SegCtl is ignored and Root TLB CCA is used. Access in root mode by other than kernel will cause an address error. H/W must set G=1 as if the access were for guest.

  • 0 Root software cannot access guest entries directly.
  • 1 Root software can access guest entries directly.

The optional ‘GuestID’ field (GuestCtl1ID or GuestCtl1_RID ) represents a unique identifier for Root and all Guest Virtual Address spaces. Each Guest’s address space is identified by a unique non-zero GuestID.

Direct root-mode access is described by GuestCtl0_DRG in Table 4.2. In the absence of this feature, root would have to probe the Root TLB with GPA, and subsequently read on match to obtain the RPA. If a miss occurs, then root must walk the guest shadow page tables in memory. Otherwise, with direct access, a miss will result in a hardware pagewalk, assuming a hardware pagewalker is supported. :book: VZ manual 4.5.1

Guest TLB Interface:

if (Instruction or Load or Store)
   GuestTLB.Key[GuestID] = GuestCtl1ID
endif
GuestTLB.Key[ASID] = Guest.EntryHiASID

martins3: great!!!. DRG used for open option tdp

In an implementation supporting GuestID (GuestCtl0G1=1), matching of guest TLB entries includes comparison of the TLB entry GuestID with the Root GuestID control field, GuestCtl1_RID.

[Martins3]

• [x] Why one CPU has to record it's guestid for every physical CPU? (every physical CPU has it's own local tlb
• [x] Only one guestid is permitted?
  • VZ manual 4.5 Virtual Memory : the pseudocode : when TLB do the translation, it read GuestCtl1_ID as guestid, searching TLB.
  • so, I guess there are multiple guestid in TLB entry, and it's necessary setup the GuestCtl1_ID in cpu when entering guest.
    • [x] what if GuestCtl1_ID is not consistent with TLB entry ? ( it means the TLB entry doesn't belong to the running guest

[Martins3]

My presumption about why after migration to a new CPU, it's necessary to clear the stale guest TLB entry in it.

[Martins3]

:book: VZ manual : TLBGWI

if IsCoprocessorEnabled(0) then
if (Config3VZ = 0) then
SignalException(ReservedInstruction, 0)
break
endif
i ← Guest.Index
if (Config4IE >= 2) then
Guest.TLB[i]hardware_invalid ← 0
if ( EntryHIEHINV=1 ) then
Guest.TLB[i]hardware_invalid ← 1
endif
endif
Guest.TLB[i]Mask ← Guest.PageMaskMask
Guest.TLB[i]R ← Guest.EntryHiR
Guest.TLB[i]VPN2 ← Guest.EntryHiVPN2 and not Guest.PageMaskMask # Impl dependent
Guest.TLB[i]ASID ← Guest.EntryHiASID
Guest.TLB[i]G ← Guest.EntryLo1G and Guest.EntryLo0G
Guest.TLB[i]PFN1 ← Guest.EntryLo1PFN and not Guest.PageMaskMask # Impl dependent
Guest.TLB[i]C1 ← Guest.EntryLo1C
Guest.TLB[i]D1 ← Guest.EntryLo1D
Guest.TLB[i]V1 ← Guest.EntryLo1V
Guest.TLB[i]PFN0 ← Guest.EntryLo0PFN and not Guest.PageMaskMask # Impl dependent
Guest.TLB[i]C0 ← Guest.EntryLo0C
Guest.TLB[i]D0 ← Guest.EntryLo0D
Guest.TLB[i]V0 ← Guest.EntryLo0V
if (GuestCtl0G1) then
Guest.TLB[i]GuestID ← GuestCtl1RID
endif
else
SignalException(CoprocessorUnusable, 0)
endif

[Martins3]

The implementation of a GuestID is recommended.Implementation complexity can be minimized by reducing the GuestID to 1 bit.

[Martins3]

GuestCtl1 register implemented. Set by hardware.
:book: vz manual table 5.2

[Martins3]

RID 23..16 Root control GuestID. Used by root TLB operations, and when GuestCtl0_DRG=1 in root mode. :book: vz manual table 5.4

• [x] I can't find the flag used for distingui guest page table and tbp page table

[Martins3]

• [ ] I don't know why much less code copied from tlb.c, I guess just because of that emulate.c use tlb.c too.