Nested register cluster in SVD file is not displayed

[Scrath1]

Hello, I have an svd file with nested register clusters. The inner cluster is not displayed when using VSCode but the exact same svd file works flawlessly in Eclipse. The specific register cluster that I am missing is called M_TTCAN (see attached images).

Is this an issue with the svd file or something that the svd viewer in cortex-debug does not support?

This is the minimal example of the SVD file which I used for making the images above:

<?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
  <vendor>Cypress Semiconductor</vendor>
  <vendorID>Cypress</vendorID>
  <name>xmc</name>
  <series>XMC</series>
  <version>1.0</version>
  <description>XMC</description>
  <licenseText></licenseText>
  <cpu>
    <name>CM7</name>
    <revision>r0p1</revision>
    <endian>little</endian>
    <mpuPresent>true</mpuPresent>
    <fpuPresent>true</fpuPresent>
    <vtorPresent>1</vtorPresent>
    <nvicPrioBits>3</nvicPrioBits>
    <vendorSystickConfig>0</vendorSystickConfig>
  </cpu>
  <addressUnitBits>8</addressUnitBits>
  <width>32</width>
  <resetValue>0x00000000</resetValue>
  <resetMask>0xFFFFFFFF</resetMask>
  <peripherals>
    <peripheral>
      <name>CANFD0</name>
      <description>CAN Controller</description>
      <headerStructName>CANFD</headerStructName>
      <baseAddress>0x40520000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>131072</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <cluster>
          <dim>5</dim>
          <dimIncrement>512</dimIncrement>
          <name>CH[%s]</name>
          <description>FIFO wrapper around M_TTCAN 3PIP, to enable DMA</description>
          <addressOffset>0x00000000</addressOffset>
          <cluster>
            <name>M_TTCAN</name>
            <description>TTCAN 3PIP, includes FD</description>
            <addressOffset>0x00000000</addressOffset>
            <register>
              <name>ENDN</name>
              <description>Endian Register</description>
              <addressOffset>0x4</addressOffset>
              <size>32</size>
              <access>read-only</access>
              <resetValue>0x87654321</resetValue>
              <resetMask>0xFFFFFFFF</resetMask>
              <fields>
                <field>
                  <name>ETV</name>
                  <description>Endianness Test Value
The endianness test value is 0x87654321.</description>
                  <bitRange>[31:0]</bitRange>
                  <access>read-only</access>
                </field>
              </fields>
            </register>
            <register>
              <name>TTCSM</name>
              <description>TT Cycle Sync Mark</description>
              <addressOffset>0x140</addressOffset>
              <size>32</size>
              <access>read-only</access>
              <resetValue>0x0</resetValue>
              <resetMask>0xFFFF</resetMask>
              <fields>
                <field>
                  <name>CSM</name>
                  <description>Cycle Sync Mark
The Cycle Sync Mark is measured</description>
                  <bitRange>[15:0]</bitRange>
                  <access>read-only</access>
                </field>
              </fields>
            </register>
          </cluster>
          <register>
            <name>RXFTOP0_STAT</name>
            <description>Receive FIFO 0 Top Status</description>
            <addressOffset>0x1A0</addressOffset>
            <size>32</size>
            <access>read-only</access>
            <resetValue>0x0</resetValue>
            <resetMask>0xFFFF</resetMask>
            <fields>
              <field>
                <name>F0TA</name>
                <description></description>
                <bitRange>[15:0]</bitRange>
                <access>read-only</access>
              </field>
            </fields>
          </register>
        </cluster>
        <register>
          <name>CTL</name>
          <description>Global CAN control register</description>
          <addressOffset>0x1000</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x0</resetValue>
          <resetMask>0x800000FF</resetMask>
          <fields>
            <field>
              <name>STOP_REQ</name>
              <description>Clock Stop Request for each TTCAN IP .
The m_ttcan_clkstop_req of each TTCAN IP is directly driven by these bits.</description>
              <bitRange>[7:0]</bitRange>
              <access>read-write</access>
            </field>
            <field>
              <name>MRAM_OFF</name>
              <description></description>
              <bitRange>[31:31]</bitRange>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
  </peripherals>
</device>

[haneefdm]

Thanks for reporting this. The SVD spec changed at some point and this went un-noticed by us.

Since version 1.3 of the specification, the nesting of elements is supported. Nested clusters express hierarchical structures of registers.

Looking into adding support for nested clusters

[haneefdm]

Since I don't have the HW, I hope you are willing to try a custom build. Can't say right now when that might be -- days or a week perhaps.

If you are in a hurry, in the meantime, there is another SVD viewer that you can try if you want. We interoperate with each other. It is Microsoft Embedded Tools

https://marketplace.visualstudio.com/items?itemName=ms-vscode.vscode-embedded-tools

In your launch.json change svdFile to svdPath and their extension will pick our debugger up. You can even use both :-) but that would be a waste of resources.

[Scrath1]

Thank you for the quick reply and for providing a temporary alternative, I am open to try the custom build whenever it is ready.

I can also confirm that the registers are displayed correctly with Microsoft Embedded Tools.

[haneefdm]

Oh, good to know.

[haneefdm]

Please try out a fix in V1.6.7-pre1 (this may get updated as additional releases are made, so download the latest)

https://github.com/Marus/cortex-debug/releases

Since I don't have any HW, can't check. The tree seems about right. However, I am skeptical of the address offsets for each register. If you can, please check them carefully.

[Scrath1]

The cluster is displayed now and the addresses seem correct. Thanks

[haneefdm]

A new release is now available in the marketplace with the fix...other changes too. It should trickle down unless auto-update is disabled or you can force an update.