search

MarvellEmbeddedProcessors / mv-ddr-marvell

20 stars 23 forks source link

need support DDR2666 #8

Closed sniperpr closed 6 years ago

sniperpr commented 6 years ago

I have make a 88f7040 board,use DDR4 2666 (MT40A1G8SA-075:E ), but mv-ddr-marvell only support to 'SPEED_BIN_DDR_2400U' on the 18.04 branch,

so, if i want use DDR4 2666 frequency， how can i do it?

thanks a lot!

`export SCP_BL2=${BASEDIR}/binaries-marvell/mrvl_scp_bl2_mss_ap_cp1_a7040.img export GCC5_AARCH64_PREFIX=${BASEDIR}/gcc5/gcc-linaro-5.3.1-2016.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu- export BL33=${BASEDIR}/edk2/Build/Armada70x0Db-AARCH64/RELEASE_GCC5/FV/ARMADA_EFI.fd export CROSS_COMPILE=${BASEDIR}/gcc5/gcc-linaro-5.3.1-2016.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-

In the ATF DIR

make distclean make clean make USE_COHERENT_MEM=0 MV_DDR_PATH=${BASEDIR}/mv-ddr LOG_LEVEL=20 PLAT=a70x0_amc all fip

/ FIXME: MISL board 2CS 8Gb x8 devices of micron - 2133P / LOG_LEVEL_INFO, 0x1, / active interfaces / / cs_mask, mirror, dqs_swap, ck_swap X subphys / { { { {0x3, 0x0, 0x0, 0x0}, {0x3, 0x0, 0x0, 0x0}, {0x3, 0x0, 0x0, 0x0}, {0x3, 0x0, 0x0, 0x0}, {0x3, 0x0, 0x0, 0x0}, {0x3, 0x0, 0x0, 0x0}, {0x3, 0x0, 0x0, 0x0}, {0x3, 0x0, 0x0, 0x0}, {0x3, 0x0, 0x0, 0x0} }, SPEED_BIN_DDR_2400P, / speed_bin / MV_DDR_DEV_WIDTH_8BIT, / sdram device width / MV_DDR_DIE_CAP_8GBIT, / die capacity / MV_DDR_FREQ_SAR, / frequency / 0, 0, / cas_l, cas_wl / MV_DDR_TEMP_LOW} }, / temperature / //MV_DDR_32BIT_ECC_PUP8_BUS_MASK, / subphys mask / BUS_MASK_32BIT, MV_DDR_CFG_DEFAULT, / ddr configuration data source / { {0} }, / raw spd data / {0} / timing parameters / };

DDR4 Training Sequence - FAILED NOTICE: Cold boot Error: image checksum verification failed Found valid image at boot postion 0x001 lNOTICE: Starting binary extension NOTICE: SVC: DEV ID: 7040, FREQ Mode: 0x19 NOTICE: SVC: AVS work point changed from 0x18 to 0x1d mv_ddr: mv_ddr-devel-18.05.0-g84dd1d9-dirty (Jul 23 2018 - 12:05:18)

Title: I/F# , Tj, Calibration_n0, Calibration_p0, Calibration_n1, Calibration_p1, Calibration_n2, Calibration_p2,CS0 , DminTx, AreaTx, DminRx, AreaRx, WL_tot, WL_ADLL, WL_PH, RL_Tot, RL_ADLL, RL_PH, RL_Smp, CenTx, CenRx, Vref, DQVref,DC-Pad0,DC-Pad1,DC-Pad2,DC-Pad3,DC-Pad4,DC-Pad5,DC-Pad6,DC-Pad7,DC-Pad8,DC-Pad9,DC-Pad10, PBSTx-Pad0,PBSTx-Pad1,PBSTx-Pad2,PBSTx-Pad3,PBSTx-Pad4,PBSTx-Pad5,PBSTx-Pad6,PBSTx-Pad7,PBSTx-Pad8,PBSTx-Pad9,PBSTx-Pad10, PBSRx-Pad0,PBSRx-Pad1,PBSRx-Pad2,PBSRx-Pad3,PBSRx-Pad4,PBSRx-Pad5,PBSRx-Pad6,PBSRx-Pad7,PBSRx-Pad8,PBSRx-Pad9,PBSRx-Pad10,CS1 , DminTx, AreaTx, DminRx, AreaRx, WL_tot, WL_ADLL, WL_PH, RL_Tot, RL_ADLL, RL_PH, RL_Smp, CenTx, CenRx, Vref, DQVref,DC-Pad0,DC-Pad1,DC-Pad2,DC-Pad3,DC-Pad4,DC-Pad5,DC-Pad6,DC-Pad7,DC-Pad8,DC-Pad9,DC-Pad10, PBSTx-Pad0,PBSTx-Pad1,PBSTx-Pad2,PBSTx-Pad3,PBSTx-Pad4,PBSTx-Pad5,PBSTx-Pad6,PBSTx-Pad7,PBSTx-Pad8,PBSTx-Pad9,PBSTx-Pad10, PBSRx-Pad0,PBSRx-Pad1,PBSRx-Pad2,PBSRx-Pad3,PBSRx-Pad4,PBSRx-Pad5,PBSRx-Pad6,PBSRx-Pad7,PBSRx-Pad8,PBSRx-Pad9,PBSRx-Pad10, Data: 0,0,11,7,6,17,20,20,CS0 , 0,0,0,0,0,0,0,0,0,0,0,0,10,3,0, 63,63,63,63,31,31,63,63,63,63,63, 31,31,31,31,0,0,31,31,31,31,31, 0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,10,3,0, 63,63,63,63,31,31,63,63,63,63,63, 31,31,31,31,0,0,31,31,31,31,31, 0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,10,3,0, 63,63,63,63,31,31,63,63,63,63,63, 31,31,31,31,0,0,31,31,31,31,31, 0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,10,3,0, 63,63,63,63,31,31,63,63,63,63,63, 31,31,31,31,0,0,31,31,31,31,31, 0,0,0,0,0,0,0,0,0,0,0,

CS1 , 0,0,0,0,0,0,0,0,0,0,0,0,10,3,0, 63,63,63,63,31,31,63,63,63,63,63, 31,31,31,31,0,0,31,31,31,31,31, 0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,10,3,0, 63,63,63,63,31,31,63,63,63,63,63, 31,31,31,31,0,0,31,31,31,31,31, 0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,10,3,0, 63,63,63,63,31,31,63,63,63,63,63, 31,31,31,31,0,0,31,31,31,31,31, 0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,10,3,0, 63,63,63,63,31,31,63,63,63,63,63, 31,31,31,31,0,0,31,31,31,31,31, 0,0,0,0,0,0,0,0,0,0,0,`

sniperpr commented 6 years ago

I has wrong, disable CS1, only enable CS0, DDR can be mv_ddr: completed successfully.

like this: tatic struct mv_ddr_topology_map board_topology_map = { 55 /* FIXME: MISL board 2CS 8Gb x8 devices of micron - 2133P */ 56 LOG_LEVEL_INFO, 57 0x1, /* active interfaces */ 58 /* cs_mask, mirror, dqs_swap, ck_swap X subphys */ 59 { { { {0x1, 0x0, 0x0, 0x0}, 60 {0x1, 0x0, 0x0, 0x0}, 61 {0x1, 0x0, 0x0, 0x0}, 62 {0x1, 0x0, 0x0, 0x0}, 63 {0x1, 0x0, 0x0, 0x0}, 64 {0x1, 0x0, 0x0, 0x0}, 65 {0x1, 0x0, 0x0, 0x0}, 66 {0x1, 0x0, 0x0, 0x0}, 67 {0x1, 0x0, 0x0, 0x0} }, 68 SPEED_BIN_DDR_1600K, /* speed_bin */ 69 MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */ 70 MV_DDR_DIE_CAP_8GBIT, /* die capacity */ 71 MV_DDR_FREQ_800, /* frequency */ 72 0, 0, /* cas_l, cas_wl */ 73 MV_DDR_TEMP_LOW} }, /* temperature */ 74 //MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */ 75 BUS_MASK_32BIT, 76 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ 77 { {0} }, /* raw spd data */ 78 {0} /* timing parameters */ 79 };

my board printf: BootROM - 2.03 Starting CP-0 IOROM 1.07 Booting from SPI NOR flash 0 (0x34) Found valid image at boot postion 0x000 lNOTICE: Starting binary extension NOTICE: SVC: DEV ID: 7040, FREQ Mode: 0x19 NOTICE: SVC: AVS work point changed from 0x22 to 0x1d mv_ddr: mv_ddr-devel-18.05.0-g84dd1d9-dirty (Jul 24 2018 - 12:15:43) rx_adjust: byte 0, alg loop 2: failed; no coverage mv_ddr: completed successfully NOTICE: Cold boot