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MasterPlayer / adxl345-sv

FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device
MIT License
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need checking about INTR signal connected correctly #17

Closed MasterPlayer closed 2 years ago

MasterPlayer commented 2 years ago

how do this : Invert INTR signal over writing to DATA_FORMAT register

MasterPlayer commented 2 years ago

Interrupt signal correctly connected : if we wrote to DATA_FORMAT register 0x20 mask -> it changes polarity of interrupt signal, in timing diagram on ILA we see it event