MasterPlayer / adxl345-sv

FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device
MIT License
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Optimal request interval calculation and assign to register in config space #45

Closed MasterPlayer closed 2 years ago

MasterPlayer commented 2 years ago

OPtimal request time calculate : CLK_PERIOD/BW_RATE

in hw we cannot realize division.

For simple, we calculate this as constant for highest bandwidth rate : OPT_REQ_INTERVAL = CLK_PERIOD/3200 and next time we do shift left arith OPT_REQ_INTERVAL, because BW_RATE values differs over previous as division of 2: 3200 1600 800 400 200 etc