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MasterPlayer / adxl345-sv

FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device
MIT License
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add register map #5

Closed MasterPlayer closed 2 years ago

MasterPlayer commented 2 years ago

Register map were formed in wiki

MasterPlayer commented 2 years ago

https://github.com/MasterPlayer/adxl345-sv/wiki#component-consists-of-two-independent-register-space