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MasterPlayer / adxl345-sv

FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device
MIT License
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Measurement testing required for Interrupt processing on software #56

Open MasterPlayer opened 2 years ago

MasterPlayer commented 2 years ago

For estimation performance we need measurements about how fastly interrupts processed in processor in classical variant and how fastly processed with this component

MasterPlayer commented 2 years ago

Full time required for interrupt from component to processor is **583 clock periods (2.915 us)**, time to transit processor from idle state to interrupt handler is **176 clock periods(880 ns)** using this component, which requests data from device and process interrupt by internal logic. Current version API perform processing without data output to terminal is **407 clock periods (2.035 us)**.

Can I improve this value? I dont know, but after estimate interrupt processing without component, i will analyze this.

MasterPlayer commented 1 year ago

изображение